Document Open Access Logo

Virtual Timing Isolation for Mixed-Criticality Systems

Authors Johannes Freitag, Sascha Uhrig, Theo Ungerer



PDF
Thumbnail PDF

File

LIPIcs.ECRTS.2018.13.pdf
  • Filesize: 0.77 MB
  • 23 pages

Document Identifiers

Author Details

Johannes Freitag
  • Airbus, Munich, Germany
Sascha Uhrig
  • Airbus, Munich, Germany
Theo Ungerer
  • University of Augsburg, Augsburg, Germany

Cite AsGet BibTex

Johannes Freitag, Sascha Uhrig, and Theo Ungerer. Virtual Timing Isolation for Mixed-Criticality Systems. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Leibniz International Proceedings in Informatics (LIPIcs), Volume 106, pp. 13:1-13:23, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2018)
https://doi.org/10.4230/LIPIcs.ECRTS.2018.13

Abstract

Commercial of the shelf multicore processors suffer from timing interferences between cores which complicates applying them in hard real-time systems like avionic applications. This paper proposes a virtual timing isolation of one main application running on one core from all other cores. The proposed technique is based on hardware external to the multicore processor and completely transparent to the main application i.e., no modifications of the software including the operating system are necessary. The basic idea is to apply a single-core execution based Worst Case Execution Time analysis and to accept a predefined slowdown during multicore execution. If the slowdown exceeds the acceptable bounds, interferences will be reduced by controlling the behavior of low-critical cores to keep the main application's progress inside the given bounds. Apart from the main goal of isolating the timing of the critical application a subgoal is also to efficiently use the other cores. For that purpose, three different mechanisms for controlling the non-critical cores are compared regarding efficient usage of the complete processor. Measuring the progress of the main application is performed by tracking the application's Fingerprint. This technology quantifies online any slowdown of execution compared to a given baseline (single-core execution). Several countermeasures to compensate unacceptable slowdowns are proposed and evaluated in this paper, together with an accuracy evaluation of the Fingerprinting. Our evaluations using the TACLeBench benchmark suite show that we can meet a given acceptable timing bound of 4 percent slowdown with a resulting real slowdown of only 3.27 percent in case of a pulse width modulated control and of 4.44 percent in the case of a frequency scaling control.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Embedded and cyber-physical systems
  • Computer systems organization → Reliability
Keywords
  • multicore
  • hard real-time systems
  • timing isolation
  • safety-critical systems
  • mixed-criticality design and assurance

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. The Nexus 5001 Forum - Standard for a Global Embedded Processor Debug Interface, 2012. Google Scholar
  2. Irune Agirre, Jaume Abella, Mikel Azkarate-Askasua, and Francisco J Cazorla. On the Tailoring of CAST-32A Certification Guidance to Real COTS Multicore Architectures. In 12th IEEE International Symposium on Industrial Embedded Systems (SIES), 2017. Google Scholar
  3. Ankit Agrawal, Gerhard Fohler, Johannes Freitag, Jan Nowotsch, Sascha Uhrig, and Michael Paulitsch. Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. In Marko Bertogna, editor, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), volume 76 of Leibniz International Proceedings in Informatics (LIPIcs), pages 2:1-2:22, Dagstuhl, Germany, 2017. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. URL: http://dx.doi.org/10.4230/LIPIcs.ECRTS.2017.2.
  4. Airbus. Future of urban mobility. 2018. http://www.airbus.com/innovation/urban-air-mobility.html. Google Scholar
  5. S. Bak, G. Yao, R. Pellizzoni, and M. Caccamo. Memory-aware scheduling of multicore task sets for real-time systems. In 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pages 300-309, Aug 2012. URL: http://dx.doi.org/10.1109/RTCSA.2012.48.
  6. G. Bernat, A. Burns, and A. Liamosi. Weakly hard real-time systems. IEEE Transactions on Computers, 50(4):308-321, Apr 2001. URL: http://dx.doi.org/10.1109/12.919277.
  7. Certification Authorities Software Team (CAST). Position Paper CAST-32A: Multi-core Processors. November 2016. URL: https://www.faa.gov/aircraft/air_cert/design_approvals/air_software/ cast/cast_papers/media/cast-32A.pdf.
  8. Tommaso Cucinotta, Fabio Checconi, Luca Abeni, and Luigi Palopoli. Self-tuning Schedulers for Legacy Real-time Applications. In Proceedings of the 5th European Conference on Computer Systems, EuroSys '10, pages 55-68, New York, NY, USA, 2010. ACM. URL: http://dx.doi.org/10.1145/1755913.1755921.
  9. Evelyn Duesterwald and Sandhya Dwarkadas. Characterizing and predicting program behavior and its variability. In In International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 220-231, 2003. Google Scholar
  10. Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann, and Simon Wegener. TACLeBench: A benchmark collection to support worst-case execution time research. In Martin Schoeberl, editor, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), volume 55 of OpenAccess Series in Informatics (OASIcs), pages 2:1-2:10, Dagstuhl, Germany, 2016. Schloss Dagstuhl-Leibniz-Zentrum für Informatik. Google Scholar
  11. Johannes Freitag and Sascha Uhrig. Dynamic interference quantification for multicore processors. In 2017 IEEE/AIAA 36th Digital Avionics Systems Conference (DASC), pages 1-6, Sept 2017. URL: http://dx.doi.org/10.1109/DASC.2017.8101991.
  12. Johannes Freitag and Sascha Uhrig. Closed Loop Controller for Multicore Real-Time Systems. In Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, and Thilo Pionteck, editors, Architecture of Computing Systems - ARCS 2018, pages 45-56, Cham, 2018. Springer International Publishing. Google Scholar
  13. Yong Fu, Nicholas Kottenstette, Chenyang Lu, and Xenofon D. Koutsoukos. Feedback Thermal Control of Real-time Systems on Multicore Processors. In Proceedings of the Tenth ACM International Conference on Embedded Software, EMSOFT '12, pages 113-122, New York, NY, USA, 2012. ACM. URL: http://dx.doi.org/10.1145/2380356.2380379.
  14. S. Girbal, X. Jean, J. Le Rhun, Daniel Gracia Pérez, and M. Gatti. Deterministic platform software for hard real-time systems using multi-core COTS. In 2015 IEEE/AIAA 34th Digital Avionics Systems Conference (DASC), pages 8D4-1-8D4-15, Sept 2015. URL: http://dx.doi.org/10.1109/DASC.2015.7311481.
  15. Kees Goossens, Martijn Koedam, Andrew Nelson, Shubhendu Sinha, Sven Goossens, Yonghui Li, Gabriela Breaban, Reinier van Kampenhout, Rasool Tavakoli, Juan Valencia, Hadi Ahmadi Balef, Benny Akesson, Sander Stuijk, Marc Geilen, Dip Goswami, and Majid Nabi. NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications, pages 491-530. Springer Netherlands, Dordrecht, 2017. URL: http://dx.doi.org/10.1007/978-94-017-7267-9_17.
  16. N. Kim, B. C. Ward, M. Chisholm, C. Y. Fu, J. H. Anderson, and F. D. Smith. Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 1-12, April 2016. URL: http://dx.doi.org/10.1109/RTAS.2016.7461323.
  17. Angeliki Kritikakou, Christine Rochange, Madeleine Faugère, Claire Pagetti, Matthieu Roy, Sylvain Girbal, and Daniel Gracia Pérez. Distributed Run-time WCET Controller for Concurrent Critical Tasks in Mixed-critical Systems. In Proceedings of the 22Nd International Conference on Real-Time Networks and Systems, RTNS '14, pages 139:139-139:148, New York, NY, USA, 2014. ACM. URL: http://dx.doi.org/10.1145/2659787.2659799.
  18. Lilium GmbH. Lilium Home Page. 2018. https://lilium.com/. Google Scholar
  19. M. Maggio, H. Hoffmann, M. D. Santambrogio, A. Agarwal, and A. Leva. Power Optimization in Embedded Systems via Feedback Control of Resource Allocation. IEEE Transactions on Control Systems Technology, 21(1):239-246, Jan 2013. URL: http://dx.doi.org/10.1109/TCST.2011.2177499.
  20. J. Nowotsch and M. Paulitsch. Leveraging multi-core computing architectures in avionics. In 2012 Ninth European Dependable Computing Conference, pages 132-143, May 2012. URL: http://dx.doi.org/10.1109/EDCC.2012.27.
  21. Jan Nowotsch, Michael Paulitsch, Daniel Buhler, Henrik Theiling, Simon Wegener, and Michael Schmidt. Multi-core interference-sensitive wcet analysis leveraging runtime resource capacity enforcement. In ECRTS, pages 109-118. IEEE Computer Society, 2014. URL: http://dx.doi.org/10.1109/ECRTS.2014.20.
  22. NXP Semiconductors. e500mc Core Reference Manual, 2013. Rev. 3. Google Scholar
  23. NXP Semiconductors. P4080 QorIQ Multicore Communication Processor Reference Manual. NXP Semiconductors, rev 2 edition, 2014. Google Scholar
  24. D. R. Sahoo, S. Swaminathan, R. Al-Omari, M. V. Salapaka, G. Manimaran, and A. K. Somani. Feedback control for real-time scheduling. In Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301), volume 2, pages 1254-1259 vol.2, May 2002. URL: http://dx.doi.org/10.1109/ACC.2002.1023192.
  25. Martin Schoeberl, Sahar Abbaspourseyedi, Alexander Jordan, Evangelia Kasapaki, Wolfgang Puffitsch, Jens Sparsø, Benny Akesson, Neil Audsley, Jamie Garside, Raffaele Capasso, Alessandro Tocchi, Kees Goossens, Sven Goossens, Yonghui Li, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Jens Knoop, Daniel Prokesch, Peter Puschner, André Rocha, and Cláudio Silva. T-crest: Time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture, 61(9):449-471, 2015. URL: http://dx.doi.org/10.1016/j.sysarc.2015.04.002.
  26. Lui Sha, Marco Caccamo, Renato Mancuso, Jung-Eun Kim, Man-Ki Yoon, Rodolfo Pellizzoni, Heechul Yun, Russel Kegley, Dennis Perlman, Greg Arundale, and Richard Bradford. Single Core Equivalent Virtual Machines for Hard Real-Time Computing on Multicore Processors. Technical report, 2014. Google Scholar
  27. T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P. G. Zaykov, Z. Petrov, B. Böddeker, S. Kehr, H. Regler, A. Hugl, C. Rochange, H. Ozaktas, H. Cassé, A. Bonenfant, P. Sainrat, I. Broster, N. Lay, D. George, E. Quiñones, M. Panic, J. Abella, F. Cazorla, S. Uhrig, M. Rohde, and A. Pyka. parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. In 2013 Euromicro Conference on Digital System Design, pages 363-370, Sept 2013. URL: http://dx.doi.org/10.1109/DSD.2013.46.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail