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A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs

Authors Marco Pagani, Enrico Rossi, Alessandro Biondi, Mauro Marinoni, Giuseppe Lipari, Giorgio Buttazzo

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Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → System on a chip
  • Hardware → Reconfigurable logic and FPGAs
Keywords
  • AXI Bus
  • Bandwidth Reservation
  • Hardware Acceleration
  • FPGA

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Abstract

Hardware platforms for real-time embedded systems are evolving towards heterogeneous architectures comprising different types of processing cores and dedicated hardware accelerators, which can be implemented on silicon or dynamically deployed on FPGA fabric. Such accelerators typically access a shared memory to exchange a significant amount of data with other processing elements. Existing COTS solutions focus on maximizing the overall throughput of the system, rather than guaranteeing the timing constraints of individual hardware accelerators. This paper presents the AXI budgeting unit (ABU), a hardware-based solution to implement a bandwidth reservation mechanism on top of the AMBA AXI standard infrastructure for hardware accelerators deployed on FPGAs. An accurate and tractable model, as well as the corresponding analysis, are also proposed to bound the response time of hardware accelerators in the presence of ABUs, in order to verify whether they can complete before their deadlines. Finally, a set of experiments are reported to evaluate the proposed approach on a state-of-the-art platform, namely the Zynq-7020 by Xilinx. The resource consumption of the ABU has been quantified to be less than 1% of the total FPGA resources of the Zynq-7020.

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Marco Pagani, Enrico Rossi, Alessandro Biondi, Mauro Marinoni, Giuseppe Lipari, and Giorgio Buttazzo. A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 24:1-24:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019) https://doi.org/10.4230/LIPIcs.ECRTS.2019.24

Author Details

Marco Pagani
  • Scuola Superiore Sant'Anna, Pisa, Italy
  • Université de Lille, CNRS, Centrale Lille, UMR 9189, CRIStAL, Lille, France
Enrico Rossi
  • Scuola Superiore Sant'Anna, Pisa, Italy
Alessandro Biondi
  • Scuola Superiore Sant'Anna, Pisa, Italy
Mauro Marinoni
  • Scuola Superiore Sant'Anna, Pisa, Italy
Giuseppe Lipari
  • Université de Lille, CNRS, Centrale Lille, UMR 9189, CRIStAL, Lille, France
Giorgio Buttazzo
  • Scuola Superiore Sant'Anna, Pisa, Italy

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