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Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms

Authors Giovani Gracioli, Rohan Tabish, Renato Mancuso, Reza Mirosanlou, Rodolfo Pellizzoni, Marco Caccamo



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Author Details

Giovani Gracioli
  • Technical University of Munich, Germany
  • Federal University of Santa Catarina, Brazil
Rohan Tabish
  • University of Illinois at Urbana-Champaign, IL, USA
Renato Mancuso
  • Boston University, MA, USA
Reza Mirosanlou
  • University of Waterloo, Canada
Rodolfo Pellizzoni
  • University of Waterloo, Canada
Marco Caccamo
  • Technical University of Munich, Germany

Acknowledgements

We would like to thank the anonymous reviewers for their valuable feedback, and our shepherd for helping to significantly improve this paper.

Cite AsGet BibTex

Giovani Gracioli, Rohan Tabish, Renato Mancuso, Reza Mirosanlou, Rodolfo Pellizzoni, and Marco Caccamo. Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 27:1-27:25, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2019)
https://doi.org/10.4230/LIPIcs.ECRTS.2019.27

Abstract

Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks. In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Embedded systems
  • Computer systems organization → Other architectures
Keywords
  • Mixed-criticality systems
  • SoC Heterogeneous platforms
  • FPGA
  • real-time computing

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