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Simultaneous Multithreading and Hard Real Time: Can It Be Safe?

Authors Sims Hill Osborne, James H. Anderson

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Author Details

Sims Hill Osborne
  • University of North Carolina, Chapel Hill, NC, USA
James H. Anderson
  • University of North Carolina, Chapel Hill, NC, USA

Funding

Work was supported by NSF grants CNS 1563845, CNS 1717589, and CPS 1837337, ARO grant W911NF-17-1-0294, ONR grant N00014-20-1-2698, and funding from General Motors.

Acknowledgements

We thank Prof. Alex Mills (Zicklin School of Business, Baruch College, New York, NY) for reviewing an early draft and offering suggestions, particularly with regards to Sec. 4. We thank Joshua Bakita (UNC-Chapel Hill) for contributions to the code used to execute our benchmark tests. Finally, we thank our anonymous reviewers and Shepherd for the improvements they suggested to the final version of this paper.

Cite AsGet BibTex

Sims Hill Osborne and James H. Anderson. Simultaneous Multithreading and Hard Real Time: Can It Be Safe?. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Leibniz International Proceedings in Informatics (LIPIcs), Volume 165, pp. 14:1-14:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)
https://doi.org/10.4230/LIPIcs.ECRTS.2020.14

Abstract

The applicability of Simultaneous Multithreading (SMT) to real-time systems has been hampered by the difficulty of obtaining reliable execution costs in an SMT-enabled system. This problem is addressed by introducing a scheduling framework, called CERT-MT, that combines scheduling-aware timing analysis with a cyclic-executive scheduler in a way that minimizes SMT-related timing variations. The proposed scheduling-aware timing analysis is based on maximum observed execution times and accounts for the uncertainty inherent in measurement-based timing analysis. The timing analysis is found to work for tasks with and without SMT, though some adjustments are required in the former case. A large-scale schedulability study is presented that shows CERT-MT can schedule systems with total utilizations approaching 1.4 times the core count, without sacrificing safety.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Real-time system specification
  • Software and its engineering → Scheduling
  • Hardware → Statistical timing analysis
  • Software and its engineering → Multithreading
Keywords
  • real-time systems
  • simultaneous multithreading
  • hard real-time
  • scheduling algorithms
  • probability
  • statistics
  • timing analysis

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References

  1. J. Abella, E. Quiñones, F. Wartel, T. Vardanega, and F. J. Cazorla. Heart of gold: Making the improbable happen to increase confidence in MBPTA. In ECRTS 2014, pages 255-265, 2014. Google Scholar
  2. S. Altmeyer, R. Douma, W. Lunniss, and R. I. Davis. Outstanding paper: Evaluation of cache partitioning for hard real-time systems. In ECRTS 2014, pages 15-26. IEEE, 2014. Google Scholar
  3. J. H. Anderson, S. Baruah, and B. Brandenburg. Multicore operating-system support for mixed criticality. In Proceedings of the Workshop on Mixed Criticality: Roadmap to Evolving UAV Certification, volume 4, page 7. Euromicro, 2009. Google Scholar
  4. B. Andersson, H. Kim, D. De Niz, M. Klein, R. Rajkumar, and J. Lehoczky. Schedulability analysis of tasks with corunner-dependent execution times. ACM Trans. Embed. Comput. Syst., 17(3):71:1-71:29, May 2018. Google Scholar
  5. T. P. Baker and A. Shaw. The cyclic executive model and ada. Real-Time Systems, 1(1):7-25, June 1989. Google Scholar
  6. A. A. Balkema and L. De Haan. Residual life time at great age. The Annals of Probability, pages 792-804, 1974. Google Scholar
  7. P. Benedicte, L. Kosmidis, E. Quinones, J. Abella, and F. J. Cazorla. A confidence assessment of wcet estimates for software time randomized caches. In INDIN, pages 90-97, 2016. Google Scholar
  8. P. Benedicte, L. Kosmidis, E. Quinones, J. Abella, and F. J. Cazorla. Modelling the confidence of timing analysis for time randomised caches. In SIES, 2016. Google Scholar
  9. B. D. Bui, M. Caccamo, L. Sha, and J. Martinez. Impact of cache partitioning on multi-tasking real time embedded systems. In RTCSA 2008, pages 101-110. IEEE, 2008. Google Scholar
  10. J. Bulpin. Operating system support for simultaneous multithreaded processors. PhD thesis, University of Cambridge, King’s College, 2005. URL: http://www.cl.com.ac.uk/TechReports/.
  11. J. Bulpin and I. Pratt. Multiprogramming performance of the Pentium 4 with hyperthreading. In Third Annual Workshop on Duplicating, Deconstruction and Debunking, pages 53-62, June 2004. Google Scholar
  12. A. Burns and S. Baruah. Migrating mixed criticality tasks within a cyclic executive framework. In J. Blieberger and M. Bader, editors, Reliable Software Technologies - Ada-Europe 2017, pages 203-216, Cham, 2017. Springer International Publishing. Google Scholar
  13. A. Burns and S. Edgar. Predicting computation time for advanced processor architectures. In ECRTS 2000, pages 89-96, February 2000. Google Scholar
  14. A. Burns, T. Fleming, and S. Baruah. Cyclic executives, multi-core platforms and mixed criticality applications. In ECRTS 2015, pages 3-12, July 2015. Google Scholar
  15. J. Carpenter, S. Funk, P. Holman, A. Srinivasan, J. H. Anderson, and S. Baruah. A categorization of real-time multiprocessor scheduling problems and algorithms. In Handbook on Scheduling Algorithms, Methods, and Models. Chapman Hall/CRC, Boca, 2004. Google Scholar
  16. F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramirez, and M. Valero. Predictable performance in SMT processors: synergy between the OS and SMTs. IEEE Transactions on Computers, 55(7):785-799, July 2006. Google Scholar
  17. F. J. Cazorla, L. Kosmidis, E. Mezzetti, C. Hernandez, J. Abella, and T. Vardanega. Probabilistic worst-case timing analysis: Taxonomy and comprehensive survey. ACM Comput. Surv., 52(1):14:1-14:35, February 2019. Google Scholar
  18. M. Chisholm, N. Kim, S. Tang, N. Otterness, J. H. Anderson, F. D. Smith, and D. E. Porter. Supporting mode changes while providing hardware isolation in mixed-criticality multicore systems. In RTNS 2017, pages 58-67. ACM, 2017. Google Scholar
  19. M. Chisholm, B. C. Ward, N. Kim, and J. H. Anderson. Cache sharing and isolation tradeoffs in multicore mixed-criticality systems. In RTSS 2015, pages 305-316. IEEE, 2015. Google Scholar
  20. R. Davis and L. Cucu-Grosjean. A survey of probabilistic timing analysis techniques for real-time systems. Leibniz Transactions on Embedded Systems, 6(1):03-1-03:60, 2019. Google Scholar
  21. C. Deutschbein, T. Fleming, A. Burns, and S. Baruah. Multi-core cyclic executives for safety-critical systems. Science of Computer Programming, 172:102-116, 2019. Google Scholar
  22. S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, R. L. Stamm, and D. M. Tullsen. Simultaneous multithreading: a platform for next-generation processors. IEEE Micro, 17(5):12-19, September 1997. Google Scholar
  23. H. Falk, S. Altmeyer, P. Hellinckx, B. Lisper, W. Puffitsch, C. Rochange, M. Schoeberl, R. B. Sørensen, P. Wägemann, and S. Wegener. TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research. In WCET 2016, volume 55, pages 2:1-2:10, 2016. Google Scholar
  24. R. A. Fisher and L. H. C. Tippett. Limiting forms of the frequency distribution of the largest or smallest member of a sample. In Mathematical Proceedings of the Cambridge Philosophical Society, volume 24, pages 180-190. Cambridge University Press, 1928. Google Scholar
  25. A. Fog. The microarchitecture of Intel, AMD, and VIA CPUs: an optimization guide for assembly programmers and compiler makers, 2018. Available at URL: https://www.agner.org/optimize/microarchitecture.pdf.
  26. T. Gomes, P. Garcia, S. Pinto, J. Monteiro, and A. Tavares. Bringing hardware multithreading to the real-time domain. IEEE Embedded Systems Letters, 8(1):2-5, March 2016. Google Scholar
  27. T. Gomes, S. Pinto, P. Garcia, and A. Tavares. RT-SHADOWS: Real-time system hardware for agnostic and deterministic OSes within softcore. In ETFA 2015, pages 1-4, September 2015. Google Scholar
  28. F. Guet, L. Santinelli, and J. Morio. On the Reliability of the Probabilistic Worst-Case Execution Time Estimates. In ERTS 2016, Toulouse, France, January 2016. Google Scholar
  29. D. Guo and R. Pellizzoni. A requests bundling DRAM controller for mixed-criticality systems. In RTAS 2017, pages 247-258. IEEE, 2017. Google Scholar
  30. M. Hassan, H. Patel, and R. Pellizzoni. A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. In RTAS 2015, pages 307-316. IEEE, 2015. Google Scholar
  31. J. L. Herman, C. J. Kenna, M. S. Mollison, J. H. Anderson, and D. M. Johnson. RTOS support for multicore mixed-criticality systems. In RTAS 2012, pages 197-208, April 2012. Google Scholar
  32. C. Hernandez, J. Abella, A. Gianarro, J. Andersson, and F. J. Cazorla. Random modulo: a new processor cache design for real-time critical systems. In Proceedings of the 53rd Annual Design Automation Conference, page 29. ACM, 2016. Google Scholar
  33. T. Hsing. On tail index estimation using dependent data. The Annals of Statistics, pages 1547-1569, 1991. Google Scholar
  34. W. Huang, J. Lin, Z. Zhang, and J.M. Chang. Performance characterization of Java applications on SMT processors. In ISPASS 2005., pages 102-111, March 2005. Google Scholar
  35. R. Jain, C. J. Hughes, and S. V. Adve. Soft real-time scheduling on simultaneous multithreaded processors. In RTSS 2002, pages 134-145, 2002. Google Scholar
  36. S. Jiménez Gil, I. Bate, G. Lima, L. Santinelli, A. Gogonel, and L. Cucu-Grosjean. Open challenges for probabilistic measurement-based worst-case execution time. IEEE Embedded Systems Letters, 9(3):69-72, September 2017. Google Scholar
  37. S. Kato, H. Kobayashi, and N. Yamasaki. U-link scheduling: bounding execution time of real-time tasks with multi-case execution time on SMT processors. In RTCSA 2005, pages 193-197, August 2005. Google Scholar
  38. S. Kato and N. Yamasaki. Extended u-link scheduling to increase the execution efficiency for SMT real-time systems. In RTCSA 2006, pages 373-377, August 2006. Google Scholar
  39. J. Kim, M. Yoon, R. Bradford, and L. Sha. Integrated modular avionics (IMA) partition scheduling with conflict-free I/O for multicore avionics systems. In 2014 IEEE 38th Annual Computer Software and Applications Conference, pages 321-331, July 2014. Google Scholar
  40. N. Kim. Combining Hardware Management with Mixed-Criticality Provisioning in Multicore Real-Time Systems. PhD thesis, UNC Chapel Hill, 2019. URL: https://www.cs.unc.edu/~anderson/diss/namhoondiss.pdf.
  41. D. B. Kirk. SMART (strategic memory allocation for real-time) cache design. In RTSS 1989, pages 229-237. IEEE, 1989. Google Scholar
  42. L. Kosmidis, J. Abella, E. Quiñones, and F. J. Cazorla. A cache design for probabilistically analysable real-time systems. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 513-518. EDA Consortium, 2013. Google Scholar
  43. L. Kosmidis, J. Abella, E. Quiñones, and F. J. Cazorla. Efficient cache designs for probabilistically analysable real-time systems. IEEE Transactions on Computers, 63(12):2998-3011, 2013. Google Scholar
  44. M. R. Leadbetter, G. Lindgren, and H. Rootzén. Conditions for the convergence in distribution of maxima of stationary normal processes. Stochastic Processes and their Applications, 8(2):131-139, 1978. Google Scholar
  45. G. Lima and I. Bate. Valid application of EVT in timing analysis by randomising execution time measurements. In RTAS 2017, pages 187-198. IEEE, 2017. Google Scholar
  46. G. Lima, D. Dias, and E. Barros. Extreme value theory for estimating task execution time bounds: A careful look. In ECRTS 2016, pages 200-211. IEEE, 2016. Google Scholar
  47. J. W. S. Liu. Real-Time Systems. Prentice Hall, New York, NY, USA, 2000. Google Scholar
  48. S. Lo, K. Lam, and T. Kuo. Real-time task scheduling for SMT systems. In RTCSA 2005, pages 5-10, August 2005. Google Scholar
  49. R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo, and R. Pellizzoni. Real-time cache management framework for multi-core architectures. In RTAS 2013, pages 45-54, April 2013. Google Scholar
  50. D. Marr, F. Binns, D. Hill, G. Hinton, K. Koufaty, J. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. In Intel Technology Journal, volume 6, pages 4-15, February 2002. Google Scholar
  51. S. Milutinovic, I. Abella, J.and Agirre, M. Azkarate-Askasua, E. Mezzetti, T. Vardanega, and F. J. Cazorla. Software time reliability in the presence of cache memories. In Ada-Europe International Conference on Reliable Software Technologies, pages 233-249. Springer, 2017. Google Scholar
  52. S. Milutinovic, J. Abella, and F. J. Cazorla. Modelling probabilistic cache representativeness in the presence of arbitrary access patterns. In 2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC), pages 142-149, May 2016. Google Scholar
  53. J. Mische, S. Uhrig, F. Kluge, and T. Ungerer. Using SMT to hide context switch times of large real-time tasksets. In RTAS 2010, pages 255-264, August 2010. Google Scholar
  54. D. Muench, M. Paulitsch, and A. Herkersdorf. Temporal separation for hardware-based I/O virtualization for mixed-criticality embedded real-time systems using PCIe SR-IOV. In ARCS 2014; 2014 Workshop Proceedings on Architecture of Computing Systems, pages 1-7, February 2014. Google Scholar
  55. B. Ocker. FAA special topics. In Collaborative Workshop: Solutions for Certification of Multicore Processors, November 2018. Google Scholar
  56. S. Osborne and J. H. Anderson. Work in progress: Combining real time and multithreading. In RTSS 2019, pages 139-142, December 2018. Google Scholar
  57. S. Osborne and J. H. Anderson. Simultaneous multithreading and hard real time: Can it be safe? (longer version with additonal material), 2020. Available at URL: http://jamesanderson.web.unc.edu/papers/.
  58. S. Osborne, J. Bakita, and J. H. Anderson. Simultaneous multithreading applied to real time. In ECRTS 2019, July 2019. Google Scholar
  59. R. Pellizzoni, B. D. Bui, M. Caccamo, and L. Sha. Coscheduling of CPU and I/O transactions in COTS-based embedded systems. In RTSS, 2008. Google Scholar
  60. J. Pickands III. Statistical inference using extreme order statistics. The Annals of Statistics, 3(1):119-131, 1975. Google Scholar
  61. L. Santinelli, F. Guet, and J. Morio. Revising measurement-based probabilistic timing analysis. In RTAS 2017, pages 199-208, 2017. Google Scholar
  62. L. Santinelli, J. Morio, G. Dufour, and D. Jacquemart. On the sustainability of the extreme value theory for WCET estimation. In 14th International Workshop on Worst-Case Execution Time Analysis. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2014. Google Scholar
  63. G. N. Seetanadi, J. Camara, L. Almeida, K. Arzen, and M. Maggio. Event-driven bandwidth allocation with formal guarantees for camera networks. In RTSS 2017, pages 243-254, December 2017. Google Scholar
  64. A. Snavely and D. M. Tullsen. Symbiotic job scheduling for a simultaneous multithreaded processor. In ASPLOS 2000, ASPLOS IX, pages 234-244, New York, NY, USA, 2000. ACM. Google Scholar
  65. K. Suito, K. Fujii, H. Matsutani, and N. Yamasaki. Dependable responsive multithreaded processor for distributed real-time systems. In 2012 IEEE COOL Chips XV, pages 1-3, April 2012. Google Scholar
  66. N. Tuck and D. M. Tullsen. Initial observations of the simultaneous multithreading Pentium 4 processor. In PACT, pages 26-35, Washington, DC, USA, 2003. IEEE Computer Society. Google Scholar
  67. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In ISCA, pages 392-403, 1995. Google Scholar
  68. P. K. Valsan, H. Yun, and F. Farshchi. Taming non-blocking caches to improve isolation in multicore real-time systems. In RTAS 2016, pages 1-12, April 2016. Google Scholar
  69. B. C. Ward, J. L. Herman, C. J. Kenna, and J. H. Anderson. Outstanding paper award: Making shared caches more predictable on multicore platforms. In ECRTS 2013, pages 157-167, July 2013. Google Scholar
  70. M. Xu, L. T. X. Phan, H. Choi, and I. Lee. Analysis and implementation of global preemptive fixed-priority scheduling with dynamic cache allocation. In RTAS 2016, pages 1-12, April 2016. Google Scholar
  71. H. Yun, R. Mancuso, Z. Wu, and R. Pellizzoni. PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In RTAS 2014, pages 155-166, April 2014. Google Scholar
  72. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In RTAS, pages 55-64, April 2013. Google Scholar
  73. M. Zimmer, D. Broman, C. Shaver, and E. A. Lee. FlexPRET: A processor platform for mixed-criticality systems. In RTAS 2014, pages 101-110, April 2014. Google Scholar
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