Analysis of Memory-Contention in Heterogeneous COTS MPSoCs

Authors Mohamed Hassan, Rodolfo Pellizzoni

Thumbnail PDF


  • Filesize: 3.46 MB
  • 24 pages

Document Identifiers

Author Details

Mohamed Hassan
  • McMaster University, Hamilton, Canada
Rodolfo Pellizzoni
  • University of Waterloo, Canada

Cite AsGet BibTex

Mohamed Hassan and Rodolfo Pellizzoni. Analysis of Memory-Contention in Heterogeneous COTS MPSoCs. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Leibniz International Proceedings in Informatics (LIPIcs), Volume 165, pp. 23:1-23:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)


Multiple-Processors Systems-on-Chip (MPSoCs) provide an appealing platform to execute Mixed Criticality Systems (MCS) with both time-sensitive critical tasks and performance-oriented non-critical tasks. Their heterogeneity with a variety of processing elements can address the conflicting requirements of those tasks. Nonetheless, the complex (and hence hard-to-analyze) architecture of Commercial-Off-The-Shelf (COTS) MPSoCs presents a challenge encumbering their adoption for MCS. In this paper, we propose a framework to analyze the memory contention in COTS MPSoCs and provide safe and tight bounds to the delays suffered by any critical task due to this contention. Unlike existing analyses, our solution is based on two main novel approaches. 1) It conducts a hybrid analysis that blends both request-level and task-level analyses into the same framework. 2) It leverages available knowledge about the types of memory requests of the task under analysis as well as contending tasks; specifically, we consider information that is already obtainable by applying existing static analysis tools to each task in isolation. Thanks to these novel techniques, our comparisons with the state-of-the art approaches show that the proposed analysis provides the tightest bounds across all evaluated access scenarios.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → System on a chip
  • Computer systems organization → Multicore architectures
  • DRAM
  • Memory
  • COTS
  • Multi-core
  • Real-Time
  • Embedded Systems
  • Analysis


  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    PDF Downloads


  1. Ankit Agrawal, Gerhard Fohler, Johannes Freitag, Jan Nowotsch, Sascha Uhrig, and Michael Paulitsch. Contention-aware dynamic memory bandwidth isolation with predictability in COTS multicores: An avionics case study. In Euromicro Conference on Real-Time Systems (ECRTS), 2017. Google Scholar
  2. Ankit Agrawal, Renato Mancuso, Rodolfo Pellizzoni, and Gerhard Fohler. Analysis of dynamic memory bandwidth regulation in multi-core real-time systems. In IEEE Real-Time Systems Symposium (RTSS), 2018. Google Scholar
  3. Balasubramanya Bhat and Frank Mueller. Making DRAM refresh predictable. In Euromicro Conference on Real-Time Systems (ECRTS), 2010. Google Scholar
  4. Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, and Ralph Wittig. UltraScale+ MPSoC and FPGA families. In IEEE Hot Chips Symposium (HCS), 2015. Google Scholar
  5. Roman Bourgade, Clément Ballabriga, Hugues Cassé, Christine Rochange, and Pascal Sainrat. Accurate analysis of memory latencies for WCET estimation. In International Conference on Real-Time and Network Systems (RTNS), 2008. Google Scholar
  6. Mauricio Calle and Ravi Ramaswami. Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem, January 2005. US Patent 6,839,797. Google Scholar
  7. Leonardo Ecco, Sebastian Tobuschat, Selma Saidi, and Rolf Ernst. A Mixed Critical Memory Controller Using Bank Privatization and Fixed Priority Scheduling. In Embedded and Real-Time Computing Systems and Applications (RTCSA), 2014. Google Scholar
  8. Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, and Lothar Thiele. Scheduling of mixed-criticality applications on resource-sharing multicore systems. In ACM International Conference on Embedded Software (EMSOFT), 2013. Google Scholar
  9. Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, and Hiren Patel. A Comparative Study of Predictable DRAM Controllers. ACM Transaction on Embedded Computer Systems (TECS), 2018. Google Scholar
  10. Danlu Guo and Rodolfo Pellizzoni. A request bundling dram controller for mixed-criticality systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2017. Google Scholar
  11. Sebastian Hahn, Michael Jacobs, and Jan Reineke. Enabling compositionality for multicore timing analysis. In International conference on real-time networks and systems (RTNS), 2016. Google Scholar
  12. Mohamed Hassan. Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities. IEEE Design & Test, 2017. Google Scholar
  13. Mohamed Hassan, Hiren Patel, and Rodolfo Pellizzoni. A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015. Google Scholar
  14. Mohamed Hassan and Rodolfo Pellizzoni. Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018. Google Scholar
  15. Intel. External memory interface handbook volume 2: Design guidelines, 2017. Google Scholar
  16. Bruce Jacob, Spencer Ng, and David Wang. Memory systems: cache, DRAM, disk. Morgan Kaufmann, 2010. Google Scholar
  17. Javier Jalle, Eduardo Quinones, Jaume Abella, Luca Fossati, Marco Zulianello, and Francisco J Cazorla. A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study. In IEEE Real-Time Systems Symposium (RTSS), 2014. Google Scholar
  18. DDR3 SDRAM JEDEC. JEDEC jesd79-3b, 2008. Google Scholar
  19. H Kim, J Lee, N Lakshminarayana, J Lim, and T Pho. Macsim: Simulator for heterogeneous architecture, 2012. Google Scholar
  20. Hyoseung Kim, Dionisio de Niz, Björn Andersson, Mark Klein, Onur Mutlu, and Ragunathan Raj Rajkumar. Bounding memory interference delay in COTS-based multi-core systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014. Google Scholar
  21. N. Kim, B. Ward, M. Chisholm, J. Anderson, and F.D. Smith. Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning. Real-Time Systems, 2017. Google Scholar
  22. Haohan Li and Sanjoy Baruah. Global mixed-criticality scheduling on multiprocessors. In Euromicro Conference on Real-Time Systems (ECRTS), 2012. Google Scholar
  23. Yonghui Li, Benny Akesson, and Kees Goossens. Dynamic Command Scheduling for Real-Time Memory Controllers. In Euromicro Conference on Real-Time Systems (ECRTS), 2014. Google Scholar
  24. Onur Mutlu and Thomas Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), pages 146-160. IEEE, 2007. Google Scholar
  25. Jan Nowotsch, Michael Paulitsch, Daniel Bühler, Henrik Theiling, Simon Wegener, and Michael Schmidt. Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In Euromicro Conference on Real-Time Systems (ECRTS), 2014. Google Scholar
  26. Xing Pan, Yasaswini Gownivaripalli, and Frank Mueller. Tintmalloc: Reducing memory access divergence via controller-aware coloring. In International Parallel and Distributed Processing Symposium (IPDPS), 2016. Google Scholar
  27. Risat Mahmud Pathan. Schedulability analysis of mixed-criticality systems on multiprocessors. In Euromicro Conference on Real-Time Systems (ECRTS), 2012. Google Scholar
  28. Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia Chen, Marco Caccamo, and Lothar Thiele. Worst case delay analysis for memory interference in multicore systems. In IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. Google Scholar
  29. Jason Poovey. Characterization of the EEMBC benchmark suite. North Carolina State University, 2007. Google Scholar
  30. Qualcomm. Qualcomm snapdragon 600e processor apq8064e recommended memory controller and device settings application note, 2016. Google Scholar
  31. Scott Rixner, William J Dally, Ujval J Kapasi, Peter Mattson, and John D Owens. Memory access scheduling. ACM SIGARCH Computer Architecture News, 28(2):128-138, 2000. Google Scholar
  32. Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. DRAMSim2: A cycle accurate memory system simulator. IEEE Computer Architecture Letters (CAL), 2011. Google Scholar
  33. Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C Hunter, and Lizy K John. Elastic refresh: Techniques to mitigate refresh penalties in high density memory. In IEEE/ACM International Symposium on Microarchitecture (MICRO), 2010. Google Scholar
  34. Prathap Kumar Valsan and Heechul Yun. MEDUSA: a predictable and high-performance DRAM controller for multicore based embedded systems. In IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA), 2015. Google Scholar
  35. Zheng Pei Wu, Rodolfo Pellizzoni, and Danlu Guo. A Composable Worst Case Latency Analysis for Multi-Rank DRAM Devices under Open Row Policy. Real-Time Systems, 2016. Google Scholar
  36. Heechul Yun, Renato Mancuso, Zheng-Pei Wu, and Rodolfo Pellizzoni. PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014. Google Scholar
  37. Heechul Yun, Rodolfo Pellizzon, and Prathap Kumar Valsan. Parallelism-aware memory interference delay analysis for COTS multicore systems. In Euromicro Conference on Real-Time Systems (ECRTS), 2015. Google Scholar
  38. Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha. MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013. Google Scholar
  39. Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha. Memory bandwidth management for efficient performance isolation in multicore platforms. IEEE Transactions on Computers (TC), 2016. Google Scholar
Questions / Remarks / Feedback

Feedback for Dagstuhl Publishing

Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail