Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual-issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
@InProceedings{schoeberl_et_al:OASIcs.PPES.2011.11, author = {Schoeberl, Martin and Schleuniger, Pascal and Puffitsch, Wolfgang and Brandner, Florian and Probst, Christian W.}, title = {{Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach}}, booktitle = {Bringing Theory to Practice: Predictability and Performance in Embedded Systems}, pages = {11--21}, series = {Open Access Series in Informatics (OASIcs)}, ISBN = {978-3-939897-28-6}, ISSN = {2190-6807}, year = {2011}, volume = {18}, editor = {Lucas, Philipp and Wilhelm, Reinhard}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PPES.2011.11}, URN = {urn:nbn:de:0030-drops-30774}, doi = {10.4230/OASIcs.PPES.2011.11}, annote = {Keywords: Time-predictable architecture, WCET analysis, WCET-aware compilation} }
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