An Automated Flow to Map Throughput Constrained Applications to a MPSoC

Authors Roel Jordans, Firew Siyoum, Sander Stuijk, Akash Kumar, Henk Corporaal

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Roel Jordans
Firew Siyoum
Sander Stuijk
Akash Kumar
Henk Corporaal

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Roel Jordans, Firew Siyoum, Sander Stuijk, Akash Kumar, and Henk Corporaal. An Automated Flow to Map Throughput Constrained Applications to a MPSoC. In Bringing Theory to Practice: Predictability and Performance in Embedded Systems. Open Access Series in Informatics (OASIcs), Volume 18, pp. 47-58, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2011)


This paper describes a design flow to map throughput constrained applications on a Multi-processor System-on-Chip (MPSoC). It integrates several state-of-the-art mapping and synthesis tools into an automated tool flow. This flow takes as input a throughput constrained application, modeled with a synchronous dataflow graph, a C-based implementation for each actor in the graph, and a template based architecture description. Using these inputs, the tool flow generates an MPSoC platform tailored to the application requirements and it subsequently maps the application to this platform. The output of the flow is an FPGA programmable bit file. An easily extensible template based architecture is presented, this architecture allows fast and flexible generation of a predictable platform that can be synthesized using the presented tool flow. The effectiveness of the tool flow is demonstrated by mapping an MJPEG-decoder onto our MPSoC platform. This case study shows that our flow is able to provide a tight, conservative bound on the worst-case throughput of the FPGA implementation. The presented tool flow is freely available at
  • design flow automation
  • multi-processor system-on-chip
  • throughput constrained
  • synchronous data-flow graphs


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