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Worst-Case Timing Estimation and Architecture Exploration in Early Design Phases

Authors Stefana Nenova, Daniel Kästner



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OASIcs.WCET.2009.2280.pdf
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Stefana Nenova
Daniel Kästner

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Stefana Nenova and Daniel Kästner. Worst-Case Timing Estimation and Architecture Exploration in Early Design Phases. In 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09). Open Access Series in Informatics (OASIcs), Volume 10, pp. 1-11, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2009)
https://doi.org/10.4230/OASIcs.WCET.2009.2280

Abstract

Selecting the right computing hardware and configuration at the beginning of an industrial project is an important and highly risky task, which is usually done without much tool support, based on experience gathered from previous projects. We present TimingExplorer - a tool to assist in the exploration of alternative system configurations in early design phases. It is based on AbsInt’s aiT WCET Analyzer and provides a parameterizable core that represents a typical architecture of interest. TimingExplorer requires (representative) source code and enables its user to take an informed decision which processor configurations are best suited for his/her needs. A suite of TimingExplorers will facilitate the process of determining what processors to use and it will reduce the risk of timing problems becoming obvious only late in the development cycle and leading to a redesign of large parts of the system.
Keywords
  • WCET estimation
  • architecture exploration WCET estimation
  • architecture exploration

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