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Instructor Selector Generation from Architecture Description

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Abstract

We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level. The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized pseudo-registers and special cases of immediate operands.

BibTeX - Entry

@InProceedings{trmac_et_al:OASIcs:2011:3061,
  author =	{Miloslav Trmac and Adam Husar and Jan Hranac and Tomas Hruska and Karel Masarik},
  title =	{{Instructor Selector Generation from Architecture Description}},
  booktitle =	{Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers},
  pages =	{109--115},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-22-4},
  ISSN =	{2190-6807},
  year =	{2011},
  volume =	{16},
  editor =	{Ludek Matyska and Michal Kozubek and Tom{\'a}{\v{s}} Vojnar and Pavel Zemc{\'i}k and David Antos},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2011/3061},
  URN =		{urn:nbn:de:0030-drops-30616},
  doi =		{http://dx.doi.org/10.4230/OASIcs.MEMICS.2010.109},
  annote =	{Keywords: LLVM, instruction generator}
}

Keywords: LLVM, instruction generator
Seminar: Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS'10) -- Selected Papers
Issue date: 2011
Date of publication: 2011


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