DARTS.4.2.5.pdf
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Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
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Part of:
Issue:
Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018)
Volume: DARTS, Volume 4 (ECOOP 2018)
Conference: Euromicro Conference on Real-Time Systems (ECRTS)
Journal: Dagstuhl Artifacts Series (DARTS) - License:
Creative Commons Attribution 3.0 Germany license
- Publication Date: 2018-06-20
Cite AsGet BibTex
Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, and Eduardo Tovar. Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 5:1-5:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
https://doi.org/10.4230/DARTS.4.2.5
https://doi.org/10.4230/DARTS.4.2.5
Artifact
DARTS-4-2-5-artifact-8dfb457b3b359cb07fa51904d24c27cc.tgz
(Filesize: 1.62 MB)
Abstract
This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
Keywords
- multiple memory controllers
- memory regulation
- multicore
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