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DARTS, Volume 4, Issue 2

Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018)

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Sebastian Altmayer
Martina Maggio

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Document
DOI: 10.4230/DARTS.4.2.0
Front Matter - ECRTS 2018 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee

Authors: Sebastian Altmayer and Martina Maggio

Abstract
Front Matter - ECRTS 2018 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee
Cite as

Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 0:i-0:ix, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{altmayer_et_al:DARTS.4.2.0,
  author =	{Altmayer, Sebastian and Maggio, Martina},
  title =	{{Front Matter - ECRTS 2018 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee}},
  pages =	{0:i--0:ix},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Altmayer, Sebastian and Maggio, Martina},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.0},
  URN =		{urn:nbn:de:0030-drops-89684},
  doi =		{10.4230/DARTS.4.2.0},
  annote =	{Keywords: Front Matter - ECRTS 2018 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee}
}
Document
DOI: 10.4230/DARTS.4.2.1
AdaptMC: A Control-Theoretic Approach for Achieving Resilience in Mixed-Criticality Systems (Artifact)

Authors: Alessandro Vittorio Papadopoulos, Enrico Bini, Sanjoy Baruah, and Alan Burns

Abstract
A system is said to be resilient if slight deviations from expected behavior during run-time does not lead to catastrophic degradation of performance: minor deviations should result in no more than minor performance degradation. In mixed-criticality systems, such degradation should additionally be criticality-cognizant. The applicability of control theory is explored for the design of resilient run-time scheduling algorithms for mixed-criticality systems. Recent results in control theory have shown how appropriately designed controllers can provide guaranteed service to hard-real-time servers; this prior work is extended to allow for such guarantees to be made concurrently to multiple criticality-cognizant servers. The applicability of this approach is explored via several experimental simulations in a dual-criticality setting. These experiments demonstrate that our control-based run-time schedulers can be synthesized in such a manner that bounded deviations from expected behavior result in the high-criticality server suffering no performance degradation and the lower-criticality one, bounded performance degradation.
Cite as

Alessandro Vittorio Papadopoulos, Enrico Bini, Sanjoy Baruah, and Alan Burns. AdaptMC: A Control-Theoretic Approach for Achieving Resilience in Mixed-Criticality Systems (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 1:1-1:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{papadopoulos_et_al:DARTS.4.2.1,
  author =	{Papadopoulos, Alessandro Vittorio and Bini, Enrico and Baruah, Sanjoy and Burns, Alan},
  title =	{{AdaptMC: A Control-Theoretic Approach for Achieving Resilience in Mixed-Criticality Systems (Artifact)}},
  pages =	{1:1--1:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Papadopoulos, Alessandro Vittorio and Bini, Enrico and Baruah, Sanjoy and Burns, Alan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.1},
  URN =		{urn:nbn:de:0030-drops-89691},
  doi =		{10.4230/DARTS.4.2.1},
  annote =	{Keywords: mixed criticality, control theory, run-time resilience, bounded overloads}
}
Document
DOI: 10.4230/DARTS.4.2.2
Using Lock Servers to Scale Real-Time Locking Protocols: Chasing Ever-Increasing Core Counts (Artifact)

Authors: Catherine E. Nemitz, Tanya Amert, and James H. Anderson

Abstract
During the past decade, parallelism-related issues have been at the forefront of real-time systems research due to the advent of multicore technologies. In the coming years, such issues will loom ever larger due to increasing core counts. Having more cores means a greater potential exists for platform capacity loss when the available parallelism cannot be fully exploited. In this work, such capacity loss is considered in the context of real-time locking protocols. In this context, lock nesting becomes a key concern as it can result in transitive blocking chains that force tasks to execute sequentially unnecessarily. Such chains can be quite long on a larger machine. Contention-sensitive real-time locking protocols have been proposed as a means of ``breaking'' transitive blocking chains, but such protocols tend to have high overhead due to more complicated lock/unlock logic. To ease such overhead, the usage of lock servers is considered herein. In particular, four specific lock-server paradigms are proposed and many nuances concerning their deployment are explored. Experiments are presented that show that, by executing cache hot, lock servers can enable reductions in lock/unlock overhead of up to 86\%. Such reductions make contention-sensitive protocols a viable approach in practice. This artifact contains the implementation of two contention-sensitive locking protocol variants implemented with four proposed lock-server paradigms, as well as the experiments with which they were evaluated.
Cite as

Catherine E. Nemitz, Tanya Amert, and James H. Anderson. Using Lock Servers to Scale Real-Time Locking Protocols: Chasing Ever-Increasing Core Counts (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 2:1-2:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{nemitz_et_al:DARTS.4.2.2,
  author =	{Nemitz, Catherine E. and Amert, Tanya and Anderson, James H.},
  title =	{{Using Lock Servers to Scale Real-Time Locking Protocols: Chasing Ever-Increasing Core Counts (Artifact)}},
  pages =	{2:1--2:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Nemitz, Catherine E. and Amert, Tanya and Anderson, James H.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.2},
  URN =		{urn:nbn:de:0030-drops-89704},
  doi =		{10.4230/DARTS.4.2.2},
  annote =	{Keywords: multiprocess locking protocols, nested locks, priority-inversion blocking, reader/writer locks, real-time locking protocols}
}
Document
DOI: 10.4230/DARTS.4.2.3
Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms (Artifact)

Authors: Waqar Ali and Heechul Yun

Abstract
This artifact is based on BWLOCK++, a software framework to protect the performance of GPU kernels from co-scheduled memory intensive CPU applications in platforms containing integrated GPUs. The artifact is designed to support the claims of the companion paper and contains instructions on how to build and execute BWLOCK++ on a target hardware platform.
Cite as

Waqar Ali and Heechul Yun. Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 3:1-3:2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{ali_et_al:DARTS.4.2.3,
  author =	{Ali, Waqar and Yun, Heechul},
  title =	{{Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms (Artifact)}},
  pages =	{3:1--3:2},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Ali, Waqar and Yun, Heechul},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.3},
  URN =		{urn:nbn:de:0030-drops-89719},
  doi =		{10.4230/DARTS.4.2.3},
  annote =	{Keywords: GPU, memory bandwidth, resource contention, CPU throttling, fair scheduler}
}
Document
DOI: 10.4230/DARTS.4.2.4
Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses (Artifact)

Authors: Paolo Pazzaglia, Luigi Pannocchi, Alessandro Biondi, and Marco Di Natale

Abstract
This document provides a brief description of the artifact material related to the paper "Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses". The code provided in the artifact implements the algorithms presented in the paper and all the experimental tests.
Cite as

Paolo Pazzaglia, Luigi Pannocchi, Alessandro Biondi, and Marco Di Natale. Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 4:1-4:2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{pazzaglia_et_al:DARTS.4.2.4,
  author =	{Pazzaglia, Paolo and Pannocchi, Luigi and Biondi, Alessandro and Di Natale, Marco},
  title =	{{Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses (Artifact)}},
  pages =	{4:1--4:2},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Pazzaglia, Paolo and Pannocchi, Luigi and Biondi, Alessandro and Di Natale, Marco},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.4},
  URN =		{urn:nbn:de:0030-drops-89728},
  doi =		{10.4230/DARTS.4.2.4},
  annote =	{Keywords: control, real-time, Cyber Physical Systems weakly hard, deadline miss, performance}
}
Document
DOI: 10.4230/DARTS.4.2.5
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)

Authors: Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, and Eduardo Tovar

Abstract
This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
Cite as

Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, and Eduardo Tovar. Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 5:1-5:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{awan_et_al:DARTS.4.2.5,
  author =	{Awan, Muhammad Ali and Souto, Pedro F. and Bletsas, Konstantinos and Akesson, Benny and Tovar, Eduardo},
  title =	{{Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)}},
  pages =	{5:1--5:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Awan, Muhammad Ali and Souto, Pedro F. and Bletsas, Konstantinos and Akesson, Benny and Tovar, Eduardo},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.5},
  URN =		{urn:nbn:de:0030-drops-89732},
  doi =		{10.4230/DARTS.4.2.5},
  annote =	{Keywords: multiple memory controllers, memory regulation, multicore}
}
Document
DOI: 10.4230/DARTS.4.2.6
Evaluations of Push Forward: Global Fixed-Priority Scheduling of Arbitrary-Deadline Sporadic Task Systems (Artifact)

Authors: Jian-Jia Chen, Georg von der Brüggen, and Niklas Ueter

Abstract
This artifact provides the experimental details and implementations of all the facilitated schedulability tests used in the reported acceptance ratio based evaluations as documented in the related paper "Push Forward: Global Fixed-Priority Scheduling of Arbitrary-Deadline Sporadic Task Systems".
Cite as

Jian-Jia Chen, Georg von der Brüggen, and Niklas Ueter. Evaluations of Push Forward: Global Fixed-Priority Scheduling of Arbitrary-Deadline Sporadic Task Systems (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 6:1-6:5, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{chen_et_al:DARTS.4.2.6,
  author =	{Chen, Jian-Jia and von der Br\"{u}ggen, Georg and Ueter, Niklas},
  title =	{{Evaluations of Push Forward: Global Fixed-Priority Scheduling of Arbitrary-Deadline Sporadic Task Systems (Artifact)}},
  pages =	{6:1--6:5},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{Chen, Jian-Jia and von der Br\"{u}ggen, Georg and Ueter, Niklas},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.6},
  URN =		{urn:nbn:de:0030-drops-89746},
  doi =		{10.4230/DARTS.4.2.6},
  annote =	{Keywords: global fixed-priority scheduling, schedulability analyses, speedup bounds}
}
Document
DOI: 10.4230/DARTS.4.2.7
Whole-System WCEC Analysis for Energy-Constrained Real-Time Systems (Artifact)

Authors: Peter Wägemann, Christian Dietrich, Tobias Distler, Peter Ulbrich, and Wolfgang Schröder-Preikschat

Abstract
Although internal devices (e.g., memory, timers) and external devices (e.g., sensors, transceivers) significantly contribute to the energy consumption of an embedded real-time system, their impact on the worst-case response energy consumption (WCRE) of tasks is usually not adequately taken into account. Most WCRE analysis techniques only focus on the processor and neglect the energy consumption of other hardware units that are temporarily activated and deactivated in the system. To solve the problem of system-wide energy-consumption analysis, we present SysWCEC, an approach that addresses these problems by enabling static WCRE analysis for entire real-time systems, including internal as well as external devices. For this purpose, SysWCEC introduces a novel abstraction, the power-state--transition graph, which contains information about the worst-case energy consumption of all possible execution paths. To construct the graph, SysWCEC decomposes the analyzed real-time system into blocks during which the set of active devices in the system does not change and is consequently able to precisely handle devices being dynamically activated or deactivated. In this artifact evaluation, which accompanies our related conference paper, we present easy to reproduce WCRE analyses with the SysWCEC framework using several benchmarks. The artifact comprises the generation of the power-state--transition graph from a given benchmark system and the formulation of an integer linear program whose solution eventually yields safe WCRE bounds.
Cite as

Peter Wägemann, Christian Dietrich, Tobias Distler, Peter Ulbrich, and Wolfgang Schröder-Preikschat. Whole-System WCEC Analysis for Energy-Constrained Real-Time Systems (Artifact). In Special Issue of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Dagstuhl Artifacts Series (DARTS), Volume 4, Issue 2, pp. 7:1-7:4, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{wagemann_et_al:DARTS.4.2.7,
  author =	{W\"{a}gemann, Peter and Dietrich, Christian and Distler, Tobias and Ulbrich, Peter and Schr\"{o}der-Preikschat, Wolfgang},
  title =	{{Whole-System WCEC Analysis for Energy-Constrained Real-Time Systems (Artifact)}},
  pages =	{7:1--7:4},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2018},
  volume =	{4},
  number =	{2},
  editor =	{W\"{a}gemann, Peter and Dietrich, Christian and Distler, Tobias and Ulbrich, Peter and Schr\"{o}der-Preikschat, Wolfgang},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.4.2.7},
  URN =		{urn:nbn:de:0030-drops-89756},
  doi =		{10.4230/DARTS.4.2.7},
  annote =	{Keywords: energy-constrained real-time systems, worst-case energy consumption (WCEC), worst-case response energy consumption (WCRE), static whole-system analysi}
}

Filters

  • Authors
  • A
  • Akesson, Benny
  • Ali, Waqar
  • Altmayer, Sebastian
  • Amert, Tanya
  • Anderson, James H.
  • Awan, Muhammad Ali
  • B
  • Baruah, Sanjoy
  • Bini, Enrico
  • Biondi, Alessandro
  • Bletsas, Konstantinos
  • Burns, Alan
  • C
  • Chen, Jian-Jia
  • D
  • Di Natale, Marco
  • Dietrich, Christian
  • Distler, Tobias
  • M
  • Maggio, Martina
  • N
  • Nemitz, Catherine E.
  • P
  • Pannocchi, Luigi
  • Papadopoulos, Alessandro Vittorio
  • Pazzaglia, Paolo
  • S
  • Schröder-Preikschat, Wolfgang
  • Souto, Pedro F.
  • T
  • Tovar, Eduardo
  • U
  • Ueter, Niklas
  • Ulbrich, Peter
  • V
  • von der Brüggen, Georg
  • W
  • Wägemann, Peter
  • Y
  • Yun, Heechul

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