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Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)

Authors Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, Giorgio Buttazzo



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Artifact Description

DARTS.6.1.4.pdf
  • Filesize: 277 kB
  • 3 pages

Document Identifiers

Author Details

Francesco Restuccia
  • TeCIP Institute and Dept. of Excellence in Robotics & AI, Scuola Superiore Sant'Anna, Pisa, Italy
Marco Pagani
  • TeCIP Institute, Scuola Superiore Sant'Anna, Pisa, Italy
  • Université de Lille, CNRS, Centrale Lille, UMR 9189, CRIStAL, Lille, France
Alessandro Biondi
  • TeCIP Institute and Dept. of Excellence in Robotics & AI, Scuola Superiore Sant'Anna, Pisa, Italy
Mauro Marinoni
  • TeCIP Institute and Dept. of Excellence in Robotics & AI, Scuola Superiore Sant'Anna, Pisa, Italy
Giorgio Buttazzo
  • TeCIP Institute and Dept. of Excellence in Robotics & AI, Scuola Superiore Sant'Anna, Pisa, Italy

Cite AsGet BibTex

Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo. Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 4:1-4:3, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2020)
https://doi.org/10.4230/DARTS.6.1.4

Artifact

Abstract

This artifact provides the means for reproducing the experiments presented in the paper "Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoC". In particular, it provides the means and describes how to replicate the experimental study that has been carried out to evaluate the proposed analysis with synthetic workloads.

Subject Classification

ACM Subject Classification
  • Hardware → Interconnect
  • Hardware → Hardware accelerators
Keywords
  • Heterogeneous computing
  • Predictable hardware acceleration
  • FPGA SoCs
  • Multi-Master architectures

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