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DARTS, Volume 6, Issue 1

Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)

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Document
Front Matter
DOI: 10.4230/DARTS.6.1.0
Front Matter, Table of Contents, Preface, Conference Organization

Authors: Alessandro V. Papadopoulos and Alessandro Biondi

Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as

Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@Article{papadopoulos_et_al:DARTS.6.1.0,
  author =	{Papadopoulos, Alessandro V. and Biondi, Alessandro},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  pages =	{0:i--0:x},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Papadopoulos, Alessandro V. and Biondi, Alessandro},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.0},
  URN =		{urn:nbn:de:0030-drops-123904},
  doi =		{10.4230/DARTS.6.1.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Artifact
DOI: 10.4230/DARTS.6.1.1
Simultaneous Multithreading and Hard Real Time: Can it be Safe? (Artifact)

Authors: Sims Hill Osborne, Joshua J. Bakita, and James H. Anderson

Abstract
The applicability of Simultaneous Multithreading (SMT) to real-time systems has been hampered by the difficulty of obtaining reliable execution costs in an SMT-enabled system. This problem is addressed from two directions. A scheduler is introduced, CERT-MT, that minimizes SMT-related timing variations, and two new timing analysis methods - one based on the binomial distribution and one based on Cantelli’s Inequality - are given. Both methods estimate probabilistic WCETs and attach statistical confidence levels to those estimates. The timing analyses are applied to tasks executing with and without SMT, and it is found that in some cases, two tasks utilizing SMT can be safely executed in less time than would be needed for either task by itself. A large-scale schedulability study is conducted, showing that CERT-MT can schedule systems with total utilizations twice what could otherwise be achieved. This artifact includes benchmark experiments used to compare execution times with and without SMT and code to analyze the benchmark experiments and duplicate the reported schedulability experiments.
Cite as

Sims Hill Osborne, Joshua J. Bakita, and James H. Anderson. Simultaneous Multithreading and Hard Real Time: Can it be Safe? (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 1:1-1:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@Article{osborne_et_al:DARTS.6.1.1,
  author =	{Osborne, Sims Hill and Bakita, Joshua J. and Anderson, James H.},
  title =	{{Simultaneous Multithreading and Hard Real Time: Can it be Safe? (Artifact)}},
  pages =	{1:1--1:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Osborne, Sims Hill and Bakita, Joshua J. and Anderson, James H.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.1},
  URN =		{urn:nbn:de:0030-drops-123915},
  doi =		{10.4230/DARTS.6.1.1},
  annote =	{Keywords: real-time systems, simultaneous multithreading, real-time, scheduling algorithms, timing analysis, probability, statistics}
}
Document
Artifact
DOI: 10.4230/DARTS.6.1.2
Demystifying the Real-Time Linux Scheduling Latency (Artifact)

Authors: Daniel Bristot de Oliveira, Daniel Casini, Rômulo Silva de Oliveira, and Tommaso Cucinotta

Abstract
The "Demystifying the Real-Time Linux Scheduling Latency" paper defines a safe bound for the real-time Linux scheduling latency. It also presents a tool kit that enables the measurements and analysis of the variables that compose the bond. The tool kit is used in the experimental section, performing the scheduling latency analyses on real platforms. This artifact provides the means to evaluate the tool kit and to reproduce the results of the experimental section.
Cite as

Daniel Bristot de Oliveira, Daniel Casini, Rômulo Silva de Oliveira, and Tommaso Cucinotta. Demystifying the Real-Time Linux Scheduling Latency (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 2:1-2:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@Article{deoliveira_et_al:DARTS.6.1.2,
  author =	{de Oliveira, Daniel Bristot and Casini, Daniel and de Oliveira, R\^{o}mulo Silva and Cucinotta, Tommaso},
  title =	{{Demystifying the Real-Time Linux Scheduling Latency (Artifact)}},
  pages =	{2:1--2:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{de Oliveira, Daniel Bristot and Casini, Daniel and de Oliveira, R\^{o}mulo Silva and Cucinotta, Tommaso},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.2},
  URN =		{urn:nbn:de:0030-drops-123928},
  doi =		{10.4230/DARTS.6.1.2},
  annote =	{Keywords: Real-time operating systems, Linux kernel, PREEMPT\underlineRT, Scheduling latency}
}
Document
Artifact
DOI: 10.4230/DARTS.6.1.3
Abstract Response-Time Analysis: A Formal Foundation for the Busy-Window Principle (Artifact)

Authors: Sergey Bozhko and Björn B. Brandenburg

Abstract
This artifact provides the means to validate and reproduce the results of the associated paper "Abstract Response-Time Analysis: A Formal Foundation for the Busy-Window Principle". In this artifact we demonstrate how to compile the source code and automatically check the proofs of each theorem. We also provide references to all key results claimed to be proven in the paper (including Abstract RTA and all eight instantiations), so that readers may confirm that no proofs have been omitted.
Cite as

Sergey Bozhko and Björn B. Brandenburg. Abstract Response-Time Analysis: A Formal Foundation for the Busy-Window Principle (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 3:1-3:2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@Article{bozhko_et_al:DARTS.6.1.3,
  author =	{Bozhko, Sergey and Brandenburg, Bj\"{o}rn B.},
  title =	{{Abstract Response-Time Analysis: A Formal Foundation for the Busy-Window Principle (Artifact)}},
  pages =	{3:1--3:2},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Bozhko, Sergey and Brandenburg, Bj\"{o}rn B.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.3},
  URN =		{urn:nbn:de:0030-drops-123930},
  doi =		{10.4230/DARTS.6.1.3},
  annote =	{Keywords: hard real-time systems, response-time analysis, uniprocessor, busy window, fixed priority, EDF, verification, Coq, Prosa, preemptive, non-preemptive, limited-preemptive}
}
Document
Artifact
DOI: 10.4230/DARTS.6.1.4
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)

Authors: Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo

Abstract
This artifact provides the means for reproducing the experiments presented in the paper "Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoC". In particular, it provides the means and describes how to replicate the experimental study that has been carried out to evaluate the proposed analysis with synthetic workloads.
Cite as

Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo. Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 4:1-4:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@Article{restuccia_et_al:DARTS.6.1.4,
  author =	{Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio},
  title =	{{Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)}},
  pages =	{4:1--4:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.4},
  URN =		{urn:nbn:de:0030-drops-123941},
  doi =		{10.4230/DARTS.6.1.4},
  annote =	{Keywords: Heterogeneous computing, Predictable hardware acceleration, FPGA SoCs, Multi-Master architectures}
}
Document
Artifact
DOI: 10.4230/DARTS.6.1.5
The Time-Triggered Wireless Architecture (Artifact)

Authors: Romain Jacob, Licong Zhang, Marco Zimmerling, Jan Beutel, Samarjit Chakraborty, and Lothar Thiele

Abstract
This artifact contains a stable version of all the data and source code required to reproduce or replicate the results presented in The Time-Triggered Wireless Architecture. One GitHub repository serves as main hub for all information related to the artifact. The README file contains detailed instructions for - Running the TTnet model - Compiling and running TTnet - Running the TTW scheduler - Reproducing the data processing - Reproducing the plots
Cite as

Romain Jacob, Licong Zhang, Marco Zimmerling, Jan Beutel, Samarjit Chakraborty, and Lothar Thiele. The Time-Triggered Wireless Architecture (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 5:1-5:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)

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@Article{jacob_et_al:DARTS.6.1.5,
  author =	{Jacob, Romain and Zhang, Licong and Zimmerling, Marco and Beutel, Jan and Chakraborty, Samarjit and Thiele, Lothar},
  title =	{{The Time-Triggered Wireless Architecture (Artifact)}},
  pages =	{5:1--5:3},
  journal =	{Dagstuhl Artifacts Series},
  ISSN =	{2509-8195},
  year =	{2020},
  volume =	{6},
  number =	{1},
  editor =	{Jacob, Romain and Zhang, Licong and Zimmerling, Marco and Beutel, Jan and Chakraborty, Samarjit and Thiele, Lothar},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.5},
  URN =		{urn:nbn:de:0030-drops-123952},
  doi =		{10.4230/DARTS.6.1.5},
  annote =	{Keywords: Time-triggered architecture, wireless bus, synchronous transmissions}
}

Filters

  • Authors
  • A
  • Anderson, James H.
  • B
  • Bakita, Joshua J.
  • Beutel, Jan
  • Biondi, Alessandro
  • Bozhko, Sergey
  • Brandenburg, Björn B.
  • Buttazzo, Giorgio
  • C
  • Casini, Daniel
  • Chakraborty, Samarjit
  • Cucinotta, Tommaso
  • D
  • de Oliveira, Daniel Bristot
  • de Oliveira, Rômulo Silva
  • J
  • Jacob, Romain
  • M
  • Marinoni, Mauro
  • O
  • Osborne, Sims Hill
  • P
  • Pagani, Marco
  • Papadopoulos, Alessandro V.
  • R
  • Restuccia, Francesco
  • T
  • Thiele, Lothar
  • Z
  • Zhang, Licong
  • Zimmerling, Marco

  • Subjects
  • Computer systems organization
  • Computer systems organization → Real-time operating systems
  • Computer systems organization → Real-time system architecture
  • Computer systems organization → Real-time system specification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Sensors and actuators
  • Hardware
  • Hardware → Hardware accelerators
  • Hardware → Interconnect
  • Networks
  • Networks → Sensor networks
  • Software and its engineering
  • Software and its engineering
  • Software and its engineering → Multithreading
  • Software and its engineering → Scheduling
  • Theory of computation
  • Theory of computation → Scheduling algorithms
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