The fault and failure models as well as their semantics within the VLSI and the distributed systems/algorithms community are quite different. Pointing out the mismatch of those fault respectively failure models is the main part of this work. The impact of the implemented failure model in terms of hardware effort and system complexity will be shown on different VLSI implementations of distributed algorithms. However, still, there are a lot of open questions left mostly related to the coverage analysis of hardware implemented fault-tolerant algorithms.
@InProceedings{fuchs:DagSemProc.08371.4, author = {Fuchs, Gottfried}, title = {{Implications of VLSI Fault Models and Distributed Systems Failure Models – A hardware designer's view}}, booktitle = {Fault-Tolerant Distributed Algorithms on VLSI Chips}, pages = {1--7}, series = {Dagstuhl Seminar Proceedings (DagSemProc)}, ISSN = {1862-4405}, year = {2009}, volume = {8371}, editor = {Bernadette Charron-Bost and Shlomi Dolev and Jo Ebergen and Ulrich Schmid}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.08371.4}, URN = {urn:nbn:de:0030-drops-19245}, doi = {10.4230/DagSemProc.08371.4}, annote = {Keywords: VLSI, fault model, distributed system, failure model} }
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