Logics Meet 1-Clock Alternating Timed Automata

Authors Shankara Narayanan Krishna, Khushraj Madnani, Paritosh K. Pandya

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Author Details

Shankara Narayanan Krishna
  • Department of Computer Science & Engineering IIT Bombay, India
Khushraj Madnani
  • Department of Computer Science & Engineering IIT Bombay, India
Paritosh K. Pandya
  • School of Technology and Computer Science, TIFR, India

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Shankara Narayanan Krishna, Khushraj Madnani, and Paritosh K. Pandya. Logics Meet 1-Clock Alternating Timed Automata. In 29th International Conference on Concurrency Theory (CONCUR 2018). Leibniz International Proceedings in Informatics (LIPIcs), Volume 118, pp. 39:1-39:17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)


This paper investigates a decidable and highly expressive real time logic QkMSO which is obtained by extending MSO[<] with guarded quantification using block of less than k metric quantifiers. The resulting logic is shown to be expressively equivalent to 1-clock ATA where loops are without clock resets, as well as, RatMTL, a powerful extension of MTL[U_I] with regular expressions. We also establish 4-variable property for QkMSO and characterize the expressive power of its 2-variable fragment. Thus, the paper presents progress towards expressively complete logics for 1-clock ATA.

Subject Classification

ACM Subject Classification
  • Theory of computation → Modal and temporal logics
  • Metric Temporal Logic
  • Alternating Timed Automata
  • MSO
  • Regular Expressions
  • Expressive Completeness


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