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Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead

Authors Pegdwende Romaric Nikiema, Angeliki Kritikakou , Marcello Traiola, Olivier Sentieys



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Pegdwende Romaric Nikiema
  • Univ Rennes, Inria, IRISA, CNRS, France
Angeliki Kritikakou
  • Univ Rennes, Inria, IRISA, CNRS, France
Marcello Traiola
  • Univ Rennes, Inria, IRISA, CNRS, France
Olivier Sentieys
  • Univ Rennes, Inria, IRISA, CNRS, France

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Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, and Olivier Sentieys. Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead. In 35th Euromicro Conference on Real-Time Systems (ECRTS 2023). Leibniz International Proceedings in Informatics (LIPIcs), Volume 262, pp. 15:1-15:22, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2023)
https://doi.org/10.4230/LIPIcs.ECRTS.2023.15

Abstract

As time-critical systems require timing guarantees, Worst-Case Execution Times (WCET) have to be employed. However, WCET estimation methods usually assume fault-free hardware. If proper actions are not taken, such fault-free WCET approaches become unsafe, when faults impact the hardware during execution. The majority of approaches, dealing with hardware faults, address the impact of faults on the functional behavior of an application, i.e., denial of service and binary correctness. Few approaches address the impact of faults on the application timing behavior, i.e., time to finish the application, and target faults occurring in memories. However, as the transistor size in modern technologies is significantly reduced, faults in cores cannot be considered negligible anymore. This work shows that faults not only affect the functional behavior, but they can have a significant impact on the timing behavior of applications. To expose the overall impact of faults, we enhance vulnerability analysis to include not only functional, but also timing correctness, and show that faults impact WCET estimations. As common techniques to deal with faults, such as watchdog timers and re-execution, have large timing overhead for error detection and correction, we propose a mechanism with near-zero and bounded timing overhead. A RISC-V core is used as a case study. The obtained results show that faults can lead up to almost 700% increase in the maximum observed execution time between fault-free and faulty execution without protection, affecting the WCET estimations. On the contrary, the proposed mechanism is able to restore fault-free WCET estimations with a bounded overhead of 2 execution cycles.

Subject Classification

ACM Subject Classification
  • General and reference → Reliability
  • General and reference → Measurement
  • Hardware → Error detection and error correction
  • Hardware → Transient errors and upsets
  • Hardware → Safety critical systems
  • Computer systems organization → Real-time system architecture
Keywords
  • Transient faults
  • Timing impact
  • Near-zero WCET error detection and correction
  • Vulnerability analysis

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