Quantum Circuit Mapping Based on Incremental and Parallel SAT Solving

Authors Jiong Yang , Yaroslav A. Kharkov, Yunong Shi , Marijn J. H. Heule , Bruno Dutertre



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Author Details

Jiong Yang
  • National University of Singapore, Singapore
Yaroslav A. Kharkov
  • AWS Quantum Technologies, New York, NY, USA
Yunong Shi
  • AWS Quantum Technologies, New York, NY, USA
Marijn J. H. Heule
  • Carnegie Mellon University, Pittsburgh, PA, USA
  • Amazon Web Services, Seattle, WA, USA
Bruno Dutertre
  • Amazon Web Services, Santa Clara, CA, USA

Acknowledgements

Part of the research was conducted during Jiong Yang’s internship at Amazon Web Services. We thank Eric Kessler and Soonho Kong for the insightful discussions on this work. We are grateful to the anonymous reviewers for their constructive comments to improve this paper.

Cite AsGet BibTex

Jiong Yang, Yaroslav A. Kharkov, Yunong Shi, Marijn J. H. Heule, and Bruno Dutertre. Quantum Circuit Mapping Based on Incremental and Parallel SAT Solving. In 27th International Conference on Theory and Applications of Satisfiability Testing (SAT 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 305, pp. 29:1-29:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
https://doi.org/10.4230/LIPIcs.SAT.2024.29

Abstract

Quantum Computing (QC) is a new computational paradigm that promises significant speedup over classical computing in various domains. However, near-term QC faces numerous challenges, including limited qubit connectivity and noisy quantum operations. To address the qubit connectivity constraint, circuit mapping is required for executing quantum circuits on quantum computers. This process involves performing initial qubit placement and using the quantum SWAP operations to relocate non-adjacent qubits for nearest-neighbor interaction. Reducing the SWAP count in circuit mapping is essential for improving the success rate of quantum circuit execution as SWAPs are costly and error-prone. In this work, we introduce a novel circuit mapping method by combining incremental and parallel solving for Boolean Satisfiability (SAT). We present an innovative SAT encoding for circuit mapping problems, which significantly improves solver-based mapping methods and provides a smooth trade-off between compilation quality and compilation time. Through comprehensive benchmarking of 78 instances covering 3 quantum algorithms on 2 distinct quantum computer topologies, we demonstrate that our method is 26× faster than state-of-the-art solver-based methods, reducing the compilation time from hours to minutes for important quantum applications. Our method also surpasses the existing heuristics algorithm by 26% in SWAP count.

Subject Classification

ACM Subject Classification
  • Software and its engineering → Compilers
  • Computer systems organization → Quantum computing
  • Computing methodologies → Artificial intelligence
Keywords
  • Quantum computing
  • Quantum compilation
  • SAT solving
  • Incremental solving
  • Parallel solving

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