Document Open Access Logo

Non-Intrusive Online Timing Analysis of Large Embedded Applications

Authors Boris Dreyer , Christian Hochberger



PDF
Thumbnail PDF

File

OASIcs.WCET.2019.2.pdf
  • Filesize: 0.89 MB
  • 11 pages

Document Identifiers

Author Details

Boris Dreyer
  • Computer Systems Group, TU Darmstadt, Germany
Christian Hochberger
  • Computer Systems Group, TU Darmstadt, Germany

Cite AsGet BibTex

Boris Dreyer and Christian Hochberger. Non-Intrusive Online Timing Analysis of Large Embedded Applications. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 2:1-2:11, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2019)
https://doi.org/10.4230/OASIcs.WCET.2019.2

Abstract

A thorough understanding of the timing behavior of embedded systems software has become very important. With the advent of ever more complex embedded software e.g. in autonomous driving, the size of this software is growing at a fast pace. Execution time profiles (ETP) have proven to be a useful way to understand the timing behavior of embedded software. Collecting these ETPs was either limited to small applications or required multiple runs of the same software for calibration processes. In this contribution, we present a novel method for collecting ETPs in a single shot of the software at very high quality even for large applications.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Computer systems organization → Embedded systems
Keywords
  • WCET
  • Execution Time Profiling
  • ARM CoreSight
  • Event Stream Processing

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. ARM Ltd. CoreSight™ Architecture Specification v2.0, 2013. ARM IHI 0029B. Google Scholar
  2. T. Ballenthin, B. Dreyer, C. Hochberger, and S. Wegener. Hardware Support for Histogram-Based Performance Analysis of Embedded Systems. In 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC), 2017. Google Scholar
  3. B. Dreyer, C. Hochberger, T. Ballenthin, and S. Wegener. Iterative Histogram-based Performance Analysis of Embedded Systems. IEEE Embedded Systems Letters, 2018. Google Scholar
  4. Boris Dreyer, Christian Hochberger, Alexander Lange, Simon Wegener, and Alexander Weiss. Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), 2016. Google Scholar
  5. Boris Dreyer, Christian Hochberger, Simon Wegener, and Alexander Weiss. Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation. In 15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015), 2015. Google Scholar
  6. Christian Ferdinand and Reinhold Heckmann. aiT: Worst-case execution time prediction by static programm analysis. In René Jacquart, editor, Building the Information Society. IFIP 18th World Computer Congress, Topical Sessions, 22-27 August 2004, Toulouse, France, pages 377-384. Kluwer, 2004. Google Scholar
  7. K. S. Gautam. Parallel Histogram Calculation for FPGA: Histogram Calculation. In 2016 IEEE 6th International Conference on Advanced Computing (IACC), pages 774-777, February 2016. URL: http://dx.doi.org/10.1109/IACC.2016.148.
  8. M. E. Ilas. New Histogram Computation Adapted for FPGA Implementation of HOG Algorithm: For Car Detection Applications. In 2017 9th Computer Science and Electronic Engineering (CEEC), 2017. Google Scholar
  9. C. Kelly, F. M. Siddiqui, B. Bardak, and R. Woods. Histogram of Oriented Gradients Front End Processing: An FPGA based Processor Approach. In 2014 IEEE Workshop on Signal Processing Systems (SiPS), 2014. Google Scholar
  10. L. Maggiani, C. Salvadori, M. Petracca, P. Pagano, and R. Saletti. Reconfigurable architecture for computing histograms in real-time tailored to FPGA-based smart camera. In 2014 IEEE 23rd International Symposium on Industrial Electronics (ISIE), pages 1042-1046, June 2014. URL: http://dx.doi.org/10.1109/ISIE.2014.6864756.
  11. E. P. R. Raj, B. S. Paul, and G. L. Narayanan. Simplified SIFT Histogram of Oriented Gradients Bin Locator on FPGA. In 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), pages 1-4, July 2018. URL: http://dx.doi.org/10.1109/ICCCNT.2018.8493928.
  12. Y. Shoshitaishvili, R. Wang, C. Salls, N. Stephens, M. Polino, A. Dutcher, J. Grosen, S. Feng, C. Hauser, C. Kruegel, and G. Vigna. SOK: (State of) The Art of War: Offensive Techniques in Binary Analysis. In 2016 IEEE Symposium on Security and Privacy (SP), pages 138-157, May 2016. Google Scholar
  13. N. Stekas and D. v. d. Heuvel. Face Recognition Using Local Binary Patterns Histograms (LBPH) on an FPGA-Based System on Chip (SoC). In 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016. Google Scholar
  14. U. K. Urimi, M. R. Kongara, and C. R. Patil. Real-time Implementation of Modified Adaptive Histogram Equalization for High Dynamic Range Infrared Images in FPGA. In 2015 Fifth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG), 2015. Google Scholar
  15. Yang Yang, Yun-Xia Liu, and Qi-Fan Dong. Sliced Integral Histogram: An Efficient Histogram Computing Algorithm and its FPGA Implementation. Multimedia Tools and Applications, 2017. Google Scholar
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail