Volume

OASIcs, Volume 72

19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)

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Event

WCET 2019, July 9, 2019, Stuttgart, Germany

Editor

Sebastian Altmeyer
  • University of Amsterdam, The Netherlands

Publication Details

  • published at: 2019-07-03
  • Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
  • ISBN: 978-3-95977-118-4
  • DBLP: db/conf/wcet/wcet2019

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Documents

No documents found matching your filter selection.
Document
Complete Volume
DOI: 10.4230/OASIcs.WCET.2019
OASIcs, Volume 72, WCET'19, Complete Volume

Authors: Sebastian Altmeyer

Abstract
OASIcs, Volume 72, WCET'19, Complete Volume
Cite as

19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@Proceedings{altmeyer:OASIcs.WCET.2019,
  title =	{{OASIcs, Volume 72, WCET'19, Complete Volume}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019},
  URN =		{urn:nbn:de:0030-drops-108667},
  doi =		{10.4230/OASIcs.WCET.2019},
  annote =	{Keywords: Theory of computation, Program analysis, Computer systems organization, Real-time systems, Software and its engineering, Software performance;}
}
Document
Front Matter
DOI: 10.4230/OASIcs.WCET.2019.0
Front Matter, Table of Contents, Preface, Conference Organization

Authors: Sebastian Altmeyer

Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as

19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 0:i-0:ix, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{altmeyer:OASIcs.WCET.2019.0,
  author =	{Altmeyer, Sebastian},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{0:i--0:ix},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.0},
  URN =		{urn:nbn:de:0030-drops-107650},
  doi =		{10.4230/OASIcs.WCET.2019.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
DOI: 10.4230/OASIcs.WCET.2019.1
TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis

Authors: Daniel Kästner, Markus Pister, Simon Wegener, and Christian Ferdinand

Abstract
Many embedded control applications have real-time requirements. If the application is safety-relevant, worst-case execution time bounds have to be determined in order to demonstrate deadline adherence. For high-performance multi-core architectures with degraded timing predictability, WCET bounds can be computed by hybrid WCET analysis which combines static analysis with timing measurements. This article focuses on a novel tool for hybrid WCET analysis based on non-intrusive instruction-level real-time tracing.
Cite as

Daniel Kästner, Markus Pister, Simon Wegener, and Christian Ferdinand. TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 1:1-1:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{kastner_et_al:OASIcs.WCET.2019.1,
  author =	{K\"{a}stner, Daniel and Pister, Markus and Wegener, Simon and Ferdinand, Christian},
  title =	{{TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{1:1--1:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.1},
  URN =		{urn:nbn:de:0030-drops-107661},
  doi =		{10.4230/OASIcs.WCET.2019.1},
  annote =	{Keywords: Worst-Case Execution Time (WCET) Analysis, Real-time Tracing, Functional Safety}
}
Document
DOI: 10.4230/OASIcs.WCET.2019.2
Non-Intrusive Online Timing Analysis of Large Embedded Applications

Authors: Boris Dreyer and Christian Hochberger

Abstract
A thorough understanding of the timing behavior of embedded systems software has become very important. With the advent of ever more complex embedded software e.g. in autonomous driving, the size of this software is growing at a fast pace. Execution time profiles (ETP) have proven to be a useful way to understand the timing behavior of embedded software. Collecting these ETPs was either limited to small applications or required multiple runs of the same software for calibration processes. In this contribution, we present a novel method for collecting ETPs in a single shot of the software at very high quality even for large applications.
Cite as

Boris Dreyer and Christian Hochberger. Non-Intrusive Online Timing Analysis of Large Embedded Applications. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 2:1-2:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{dreyer_et_al:OASIcs.WCET.2019.2,
  author =	{Dreyer, Boris and Hochberger, Christian},
  title =	{{Non-Intrusive Online Timing Analysis of Large Embedded Applications}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{2:1--2:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.2},
  URN =		{urn:nbn:de:0030-drops-107674},
  doi =		{10.4230/OASIcs.WCET.2019.2},
  annote =	{Keywords: WCET, Execution Time Profiling, ARM CoreSight, Event Stream Processing}
}
Document
DOI: 10.4230/OASIcs.WCET.2019.3
ePAPI: Performance Application Programming Interface for Embedded Platforms

Authors: Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Enrique Fernández, and Francisco J. Cazorla

Abstract
Performance Monitoring Counters (PMCs) have been traditionally used in the mainstream computing domain to perform debugging and optimization of software performance. PMCs are increasingly considered in embedded time-critical domains to collect in-depth information, e.g. cache misses and memory accesses, of software execution time on complex multicore platforms. In main-stream platforms, standardized specifications and applications like the Performance Application Programming Interface (PAPI) and perf have been proposed to deal with variable PMC support across platforms, by providing a shared interface for configuring and collecting traceable events. However, no equivalent solution exists for embedded critical processors for which the user is required to deal with low-level, platform-specific, and error-prone manipulation of PMC registers. In this paper, we address the need for a standardized PMC interface in the embedded domain, especially in view to support timing characterization of embedded platforms. We assess the compatibility of the PAPI interface with the PMC support available on the AURIX TC297, a reference automotive platform, and we implement and validate ePAPI, the first functionally-equivalent and low-overhead implementation of PAPI for the considered embedded platform.
Cite as

Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Enrique Fernández, and Francisco J. Cazorla. ePAPI: Performance Application Programming Interface for Embedded Platforms. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 3:1-3:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{giesen_et_al:OASIcs.WCET.2019.3,
  author =	{Giesen, Jeremy and Mezzetti, Enrico and Abella, Jaume and Fern\'{a}ndez, Enrique and Cazorla, Francisco J.},
  title =	{{ePAPI: Performance Application Programming Interface for Embedded Platforms}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{3:1--3:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.3},
  URN =		{urn:nbn:de:0030-drops-107682},
  doi =		{10.4230/OASIcs.WCET.2019.3},
  annote =	{Keywords: Monitoring counters, embedded systems}
}
Document
DOI: 10.4230/OASIcs.WCET.2019.4
Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems

Authors: Phillip Raffeck, Christian Eichler, Peter Wägemann, and Wolfgang Schröder-Preikschat

Abstract
Many energy-constrained cyber-physical systems require both timeliness and the execution of tasks within given energy budgets. That is, besides knowledge on worst-case execution time (WCET), the worst-case energy consumption (WCEC) of operations is essential. Unfortunately, WCET analysis approaches are not directly applicable for deriving WCEC bounds in device-driven cyber-physical systems: For example, a single memory operation can lead to a significant power-consumption increase when thereby switching on a device (e.g. transceiver, actuator) in the embedded system. However, as we demonstrate in this paper, existing approaches from microarchitecture-aware timing analysis (i.e. considering cache and pipeline effects) are beneficial for determining WCEC bounds: We extended our framework on whole-system analysis with microarchitecture-aware timing modeling to precisely account for the execution time that devices are kept (in)active. Our evaluations based on a benchmark generator, which is able to output benchmarks with known baselines (i.e. actual WCET and actual WCEC), and an ARM Cortex-M4 platform validate that the approach significantly reduces analysis pessimism in whole-system WCEC analyses.
Cite as

Phillip Raffeck, Christian Eichler, Peter Wägemann, and Wolfgang Schröder-Preikschat. Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 4:1-4:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{raffeck_et_al:OASIcs.WCET.2019.4,
  author =	{Raffeck, Phillip and Eichler, Christian and W\"{a}gemann, Peter and Schr\"{o}der-Preikschat, Wolfgang},
  title =	{{Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{4:1--4:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.4},
  URN =		{urn:nbn:de:0030-drops-107699},
  doi =		{10.4230/OASIcs.WCET.2019.4},
  annote =	{Keywords: WCEC, WCRE, WCET, michroarchitecture analysis, whole-system analysis}
}
Document
DOI: 10.4230/OASIcs.WCET.2019.5
WCET of OCaml Bytecode on Microcontrollers: An Automated Method and Its Formalisation

Authors: Steven Varoumas and Tristan Crolard

Abstract
Considering the bytecode representation of a program written in a high-level programming language enables portability of its execution as well as a factorisation of various possible analyses of this program. In this article, we present a method for computing the worst-case execution time (WCET) of an embedded bytecode program fit to run on a microcontroller. Due to the simple memory model of such a device, this automated WCET computation relies only on a control-flow analysis of the program, and can be adapted to multiple models of microcontrollers. This method evaluates the bytecode program using concrete as well as partially unknown values, in order to estimate its longest execution time. We present a software tool, based on this method, that computes the WCET of a synchronous embedded OCaml program. One key contribution of this article is a mechanically checked formalisation of the aforementioned method over an idealised bytecode language, as well as its proof of correctness.
Cite as

Steven Varoumas and Tristan Crolard. WCET of OCaml Bytecode on Microcontrollers: An Automated Method and Its Formalisation. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 5:1-5:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{varoumas_et_al:OASIcs.WCET.2019.5,
  author =	{Varoumas, Steven and Crolard, Tristan},
  title =	{{WCET of OCaml Bytecode on Microcontrollers: An Automated Method and Its Formalisation}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{5:1--5:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.5},
  URN =		{urn:nbn:de:0030-drops-107702},
  doi =		{10.4230/OASIcs.WCET.2019.5},
  annote =	{Keywords: Worst-case execution time, microcontrollers, synchronous programming, bytecode, OCaml}
}
Document
DOI: 10.4230/OASIcs.WCET.2019.6
Validating Static WCET Analysis: A Method and Its Application

Authors: Wei-Tsun Sun, Eric Jenn, and Hugues Cassé

Abstract
WCET analysis is a key activity in the development of safety critical real-time systems. Whether upper bounds on WCETs are obtained using static analysis or measurements, the confidence on the compliance of a system with its temporal requirements directly depends on the confidence on these estimations. Static WCET analysis based on abstract interpretation takes benefits from its formal foundations. However, it also strongly depends on the correctness of the underlying models. We hereby show how we have validated the version of the data flow static analyser of OTAWA applied to the AURIX TC275 target processor.
Cite as

Wei-Tsun Sun, Eric Jenn, and Hugues Cassé. Validating Static WCET Analysis: A Method and Its Application. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 6:1-6:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{sun_et_al:OASIcs.WCET.2019.6,
  author =	{Sun, Wei-Tsun and Jenn, Eric and Cass\'{e}, Hugues},
  title =	{{Validating Static WCET Analysis: A Method and Its Application}},
  booktitle =	{19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019)},
  pages =	{6:1--6:10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-118-4},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{72},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2019.6},
  URN =		{urn:nbn:de:0030-drops-107713},
  doi =		{10.4230/OASIcs.WCET.2019.6},
  annote =	{Keywords: validation of WCET tools, ISS, nML}
}

Filters

  • Authors
  • A
  • Abella, Jaume
  • Altmeyer, Sebastian
  • C
  • Cassé, Hugues
  • Cazorla, Francisco J.
  • Crolard, Tristan
  • D
  • Dreyer, Boris
  • E
  • Eichler, Christian
  • F
  • Ferdinand, Christian
  • Fernández, Enrique
  • G
  • Giesen, Jeremy
  • H
  • Hochberger, Christian
  • J
  • Jenn, Eric
  • K
  • Kästner, Daniel
  • M
  • Mezzetti, Enrico
  • P
  • Pister, Markus
  • R
  • Raffeck, Phillip
  • S
  • Schröder-Preikschat, Wolfgang
  • Sun, Wei-Tsun
  • V
  • Varoumas, Steven
  • W
  • Wägemann, Peter
  • Wegener, Simon

  • Subjects
  • Computer systems organization
  • Computer systems organization → Embedded and cyber-physical systems
  • Computer systems organization → Embedded software
  • Computer systems organization → Embedded systems
  • Computer systems organization → Real-time systems
  • Hardware
  • Hardware → Power and energy
  • Hardware → Static timing analysis
  • Software and its engineering
  • Software and its engineering → Real-time schedulability
  • Software and its engineering → Software performance
  • Software and its engineering → Software verification and validation
  • Theory of computation
  • Theory of computation → Program analysis
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