Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems

Authors Phillip Raffeck, Christian Eichler, Peter Wägemann, Wolfgang Schröder-Preikschat

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Author Details

Phillip Raffeck
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Christian Eichler
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Peter Wägemann
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Wolfgang Schröder-Preikschat
  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany


We thank Simon Schuster for his insightful comments and the support with Platin’s source base. We also thank Dominik Huber, Aaron Strahlberger, and Julius Wiedmann for their help with reducing the pessimism of the microarchitecture analysis.

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Phillip Raffeck, Christian Eichler, Peter Wägemann, and Wolfgang Schröder-Preikschat. Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems. In 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019). Open Access Series in Informatics (OASIcs), Volume 72, pp. 4:1-4:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)


Many energy-constrained cyber-physical systems require both timeliness and the execution of tasks within given energy budgets. That is, besides knowledge on worst-case execution time (WCET), the worst-case energy consumption (WCEC) of operations is essential. Unfortunately, WCET analysis approaches are not directly applicable for deriving WCEC bounds in device-driven cyber-physical systems: For example, a single memory operation can lead to a significant power-consumption increase when thereby switching on a device (e.g. transceiver, actuator) in the embedded system. However, as we demonstrate in this paper, existing approaches from microarchitecture-aware timing analysis (i.e. considering cache and pipeline effects) are beneficial for determining WCEC bounds: We extended our framework on whole-system analysis with microarchitecture-aware timing modeling to precisely account for the execution time that devices are kept (in)active. Our evaluations based on a benchmark generator, which is able to output benchmarks with known baselines (i.e. actual WCET and actual WCEC), and an ARM Cortex-M4 platform validate that the approach significantly reduces analysis pessimism in whole-system WCEC analyses.

Subject Classification

ACM Subject Classification
  • Hardware → Static timing analysis
  • Hardware → Power and energy
  • Computer systems organization → Embedded and cyber-physical systems
  • WCEC
  • WCRE
  • WCET
  • michroarchitecture analysis
  • whole-system analysis


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