Document Open Access Logo

Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters

Authors Cédric Cazanove , Benjamin Lesage , Frédéric Boniol , Jérôme Ermont

PDF

File

Thumbnail PDF
PDF
OASIcs.WCET.2024.3.pdf
  • Filesize: 0.7 MB
  • 12 pages

Document Identifiers

Subject Classification

ACM Subject Classification
  • Computer systems organization → Embedded hardware
  • Computer systems organization → System on a chip
  • Computer systems organization → Real-time system architecture
  • Computer systems organization → Multicore architectures
Keywords
  • GPU
  • benchmarks
  • simulation
  • certification

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads
    0
    Metadata Views

Abstract

The certification objectives for airborne electronic hardware defined in AMC20-152A [EASA, 2021] and in AMC20-193 [EASA, 2020] capture some of the activities required for an applicant to embed a hardware platform in a safety-critical avionic system. For COTS (Commercially available Off-The-Shelf) platforms in particular, these objectives require applicants to identify functions, configuration settings, and resources present on the platform, and assess their use by the system. AMC20-152A however recognizes that documentation regarding the behavior of a COTS may be incomplete.
There is thus a strong push for applicants to the certification of a COTS to demonstrate their mastery of the platform, to highlight relevant factors (functions, settings, resources, etc.), and their use in their system. We outline in the following a standard approach to the exploration of unchecked factors of a platform, considering existing approaches in the literature, to build such a mastery. Our approach incrementally incorporates and validates knowledge of various factors by including them in micro-simulations compared to experimental ground truth.

Cite As Get BibTex

Cédric Cazanove, Benjamin Lesage, Frédéric Boniol, and Jérôme Ermont. Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024) https://doi.org/10.4230/OASIcs.WCET.2024.3

Author Details

Cédric Cazanove
  • ONERA, Toulouse, France
Benjamin Lesage
  • ONERA, Toulouse, France
Frédéric Boniol
  • ONERA, Toulouse, France
Jérôme Ermont
  • IRIT - INP - ENSEEIHT, Toulouse, France

Funding

The work presented in this paper is part of the PHYLOG 2 project supported by the Directorate General of Civil Aviation (DGAC). It is funded by the French government through the France Relance program, based on the funding from the European Union through the NextGenerationEU program.

References

  1. Michaël Adalbert, Thomas Carle, and Christine Rochange. PasTiS: building an NVIDIA Pascal GPU simulator for embedded AI applications. In 11th European Congress on Embedded Real-Time Systems (ERTS 2022), 2022. URL: https://ut3-toulouseinp.hal.science/hal-03684680.
  2. Alif Ahmed and Kevin Skadron. Hopscotch: a micro-benchmark suite for memory performance evaluation. In Proceedings of the International Symposium on Memory Systems, MEMSYS '19, pages 167-172, 2019. URL: https://doi.org/10.1145/3357526.3357574.
  3. Tanya Amert. Enabling Real-Time Certification of Autonomous Driving Applications. PhD thesis, The University of North Carolina at Chapel Hill, 2021. AAI28650154. Google Scholar
  4. Tanya Amert, Zelin Tong, Sergey Voronov, Joshua Bakita, F. Donelson Smith, and James H. Anderson. TimeWall: Enabling Time Partitioning for Real-Time Multicore+Accelerator Platforms. In 2021 IEEE Real-Time Systems Symposium (RTSS), pages 455-468, 2021. URL: https://doi.org/10.1109/RTSS52674.2021.00048.
  5. Ali Bakhoda, George Yuan, Wilson Fung, Henry Wong, and Tor Aamodt. Analyzing CUDA workloads using a detailed GPU simulator. In IEEE International Symposium on Performance Analysis of Systems and Software, pages 163-174, 2009. URL: https://doi.org/10.1109/ISPASS.2009.4919648.
  6. Joshua Bakita and James H. Anderson. Hardware Compute Partitioning on NVIDIA GPUs. 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 54-66, 2023. URL: https://api.semanticscholar.org/CorpusID:259235797.
  7. Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J. Cazorla, and Peio Onaindia. Gmai: Understanding and exploiting the internals of gpu resource allocation in critical systems. ACM Trans. Embed. Comput. Syst., 19(5), September 2020. URL: https://doi.org/10.1145/3391896.
  8. EASA. AMC (Acceptable Means of Compliance) 20-193 on the use of multi-core processors (MCPs), 2020. Google Scholar
  9. EASA. AMC (Acceptable Means of Compliance) 20-152A Development Assurance for Airborne Electronic Hardware (AEH), 2021. Google Scholar
  10. Zhe Jia, Marco Maggioni, Benjamin Staiger, and Daniele Paolo Scarpazza. Dissecting the NVIDIA volta GPU architecture via microbenchmarking. CoRR, abs/1804.06826, 2018. URL: https://arxiv.org/abs/1804.06826.
  11. NVIDIA. Jetson AGX xavier 32 GB specs. URL: https://www.techpowerup.com/gpu-specs/jetson-agx-xavier-32-gb.c4088.
  12. NVIDIA. Volta tuning guide. URL: https://docs.nvidia.com/cuda/volta-tuning-guide/.
  13. NVIDIA. NVIDIA Xavier Series System-on-Chip: Technical Reference Manual. NVIDIA Corporation, Santa Clara, California, April 2020. Google Scholar
  14. NVIDIA. Nvidia heterogeneous computing on cuda platforms. https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#heterogeneous-computing, 2022. Accessed: 2022-11.
  15. Ignacio Sañudo Olmedo, Nicola Capodieci, Jorge Luis Martinez, Andrea Marongiu, and Marko Bertogna. Dissecting the CUDA scheduling hierarchy: a Performance and Predictability Perspective. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 213-225, 2020. URL: https://doi.org/10.1109/RTAS48715.2020.000-5.
  16. Nathan Otterness, Ming Yang, Tanya Amert, James H. Anderson, and F. D. Smith. Inferring the scheduling policies of an embedded CUDA GPU. In Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT), 2017. Google Scholar
  17. Nathan Michael Otterness. Developing Real-Time GPU-Sharing Platforms for Artificial-Intelligence Applications. PhD thesis, The University of North Carolina at Chapel Hill, 2022. Google Scholar
  18. Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely, and Joel Emer. Adaptive insertion policies for high performance caching. In Proceedings of the 34th Annual International Symposium on Computer Architecture, ISCA '07, 2007. URL: https://doi.org/10.1145/1250662.1250709.
  19. Tyler Yandrofski, Jingyuan Chen, Nathan Otterness, James H. Anderson, and F. Donelson Smith. Making Powerful Enemies on NVIDIA GPUs. In 2022 IEEE Real-Time Systems Symposium (RTSS), pages 383-395, 2022. URL: https://doi.org/10.1109/RTSS55097.2022.00040.
  20. Ming Yang, Nathan Otterness, Tanya Amert, Joshua Bakita, James H. Anderson, and F. Donelson Smith. Avoiding Pitfalls when Using NVIDIA GPUs for Real-Time Tasks in Autonomous Systems. In ECRTS, 2018. Google Scholar
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail
© 2023-2025 Schloss Dagstuhl – LZI GmbH About DROPS Imprint Privacy Contact