Volume
OASIcs, Volume 121
22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)
-
Part of:
Series:
Open Access Series in Informatics (OASIcs)
Conference: Workshop on Worst-Case Execution Time Analysis (WCET)
Event
WCET 2024, July 9, 2024, Lille, FranceEditor
Publication Details
- published at: 2024-07-26
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-346-1
- DBLP: db/conf/wcet/wcet2024
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Document
Complete Volume
OASIcs, Volume 121, WCET 2024, Complete Volume
Abstract
OASIcs, Volume 121, WCET 2024, Complete Volume
Cite as
22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 1-88, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@Proceedings{carle:OASIcs.WCET.2024,
title = {{OASIcs, Volume 121, WCET 2024, Complete Volume}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {1--88},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024},
URN = {urn:nbn:de:0030-drops-204673},
doi = {10.4230/OASIcs.WCET.2024},
annote = {Keywords: OASIcs, Volume 121, WCET 2024, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{carle:OASIcs.WCET.2024.0,
author = {Carle, Thomas},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.0},
URN = {urn:nbn:de:0030-drops-204682},
doi = {10.4230/OASIcs.WCET.2024.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
WORTEX: Worst-Case Execution Time and Energy Estimation in Low-Power Microprocessors Using Explainable ML
Abstract
Real-time and energy-constrained systems heavily rely on estimates of the worst-case execution time (WCET) and worst-case energy consumption (WCEC) of code snippets to ensure trustworthy operation. Designing architecture-specific analytical models for time and energy is often challenging and time-consuming. In situations where analytical models are unavailable or incomplete, machine learning (ML) techniques emerge as a promising solution to build WCEC/WCET models. This paper introduces WORTEX, a toolkit for WCEC/WCET estimation of basic blocks based on ML techniques. To ensure the real-world applicability of its models, WORTEX extracts large datasets of basic blocks from real programs and precisely measures their energy consumption/execution time on the physical target platform. The dataset is used to train various WCEC/WCET models using different ML techniques. Experimental results on simple and time-predictable hardware show that even the most basic ML techniques provide accurate results, that never underestimate actual values. We also discuss the use of explainability techniques to gain trustworthiness for the models.
Cite as
Hugo Reymond, Abderaouf Nassim Amalou, and Isabelle Puaut. WORTEX: Worst-Case Execution Time and Energy Estimation in Low-Power Microprocessors Using Explainable ML. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 1:1-1:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{reymond_et_al:OASIcs.WCET.2024.1,
author = {Reymond, Hugo and Amalou, Abderaouf Nassim and Puaut, Isabelle},
title = {{WORTEX: Worst-Case Execution Time and Energy Estimation in Low-Power Microprocessors Using Explainable ML}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {1:1--1:14},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.1},
URN = {urn:nbn:de:0030-drops-204691},
doi = {10.4230/OASIcs.WCET.2024.1},
annote = {Keywords: Worst-Case Execution Time (WCET), Worst-Case Energy Consumption (WCEC), Machine Learning, Explainable ML models}
}
Document
The Platin Multi-Target Worst-Case Analysis Tool
Abstract
With the increasing number of applications that require reliable runtime guarantees, the relevance of static worst-case analysis tools that can provide such guarantees increases. These analysis tools determine resource-consumption bounds of application tasks, with a model of the underlying hardware, to meet given resource budgets during runtime, such as deadlines of real-time tasks.
This paper presents enhancements to the Platin worst-case analysis tool developed since its original release more than ten years ago. These novelties comprise Platin’s support for new architectures (i.e., ARMv6-M, RISC-V, and AVR) in addition to the previous backends for Patmos and ARMv7-M. Further, Platin now features system-wide analysis methods and annotation support to express system-level constraints. Besides an overview of these enhancements, we evaluate Platin’s accuracy for the two supported architecture implementations, Patmos and RISC-V.
Cite as
Emad Jacob Maroun, Eva Dengler, Christian Dietrich, Stefan Hepp, Henriette Herzog, Benedikt Huber, Jens Knoop, Daniel Wiltsche-Prokesch, Peter Puschner, Phillip Raffeck, Martin Schoeberl, Simon Schuster, and Peter Wägemann. The Platin Multi-Target Worst-Case Analysis Tool. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 2:1-2:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{maroun_et_al:OASIcs.WCET.2024.2,
author = {Maroun, Emad Jacob and Dengler, Eva and Dietrich, Christian and Hepp, Stefan and Herzog, Henriette and Huber, Benedikt and Knoop, Jens and Wiltsche-Prokesch, Daniel and Puschner, Peter and Raffeck, Phillip and Schoeberl, Martin and Schuster, Simon and W\"{a}gemann, Peter},
title = {{The Platin Multi-Target Worst-Case Analysis Tool}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {2:1--2:14},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.2},
URN = {urn:nbn:de:0030-drops-204704},
doi = {10.4230/OASIcs.WCET.2024.2},
annote = {Keywords: worst-case resource consumption, WCET, static analysis tool}
}
Document
Invited Paper
Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters
Abstract
The certification objectives for airborne electronic hardware defined in AMC20-152A [EASA, 2021] and in AMC20-193 [EASA, 2020] capture some of the activities required for an applicant to embed a hardware platform in a safety-critical avionic system. For COTS (Commercially available Off-The-Shelf) platforms in particular, these objectives require applicants to identify functions, configuration settings, and resources present on the platform, and assess their use by the system. AMC20-152A however recognizes that documentation regarding the behavior of a COTS may be incomplete.
There is thus a strong push for applicants to the certification of a COTS to demonstrate their mastery of the platform, to highlight relevant factors (functions, settings, resources, etc.), and their use in their system. We outline in the following a standard approach to the exploration of unchecked factors of a platform, considering existing approaches in the literature, to build such a mastery. Our approach incrementally incorporates and validates knowledge of various factors by including them in micro-simulations compared to experimental ground truth.
Cite as
Cédric Cazanove, Benjamin Lesage, Frédéric Boniol, and Jérôme Ermont. Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{cazanove_et_al:OASIcs.WCET.2024.3,
author = {Cazanove, C\'{e}dric and Lesage, Benjamin and Boniol, Fr\'{e}d\'{e}ric and Ermont, J\'{e}r\^{o}me},
title = {{Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {3:1--3:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.3},
URN = {urn:nbn:de:0030-drops-204719},
doi = {10.4230/OASIcs.WCET.2024.3},
annote = {Keywords: GPU, benchmarks, simulation, certification}
}
Document
Invited Paper
Invited Paper: Worst-Case Execution Time Analysis of Lingua Franca Applications
Abstract
Real-time systems need to prove that all deadlines will be met. To enable this proof, the full stack of the system must be analyzable, and the right tools must be available. This includes the processor (execution platform), the runtime system, the compiler, and the WCET analysis tool.
This paper presents a combination of the time-predictable processor Patmos, the coordination language Lingua Franca, and the WCET analysis tool Platin. We show how carefully written Lingua Franca programs enable static WCET analysis to build safety-critical applications.
Cite as
Martin Schoeberl, Ehsan Khodadad, Shaokai Lin, Emad Jacob Maroun, Luca Pezzarossa, and Edward A. Lee. Invited Paper: Worst-Case Execution Time Analysis of Lingua Franca Applications. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 4:1-4:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{schoeberl_et_al:OASIcs.WCET.2024.4,
author = {Schoeberl, Martin and Khodadad, Ehsan and Lin, Shaokai and Maroun, Emad Jacob and Pezzarossa, Luca and Lee, Edward A.},
title = {{Invited Paper: Worst-Case Execution Time Analysis of Lingua Franca Applications}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {4:1--4:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.4},
URN = {urn:nbn:de:0030-drops-204721},
doi = {10.4230/OASIcs.WCET.2024.4},
annote = {Keywords: worst-case execution time, coordination language, real-time systems, lingua franca}
}
Document
Invited Paper
Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip
Abstract
Main memory sharing in commercial, FPGA-based Heterogeneous System on Chips (HeSoCs) can cause significant interference, and ultimately severe slowdown of the executing workload, which bars the adoption of such systems in the context of time-critical applications. Bandwidth regulation approaches based on monitoring and throttling are widely adopted also in commercial hardware to improve the system quality of service (QoS), and previous work has shown that the finer the granularity of the mechanism, the more effective the QoS control. Different mechanisms, however, might exploit more or less effectively the available residual memory bandwidth, provided that the QoS requirement is satisfied. In this paper we present an exhaustive experimental evaluation of how three bandwidth regulation mechanisms with coarse, fine and ultra-fine granularity compare in terms of exploitation of the system memory bandwidth. Our results show that a very fine-grained regulation mechanism might experience worse system-level memory bandwidth exploitation compared to a coarser-grained approach.
Cite as
Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Tania Di Mascio, and Andrea Marongiu. Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 5:1-5:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{brilli_et_al:OASIcs.WCET.2024.5,
author = {Brilli, Gianluca and Valente, Giacomo and Capotondi, Alessandro and Di Mascio, Tania and Marongiu, Andrea},
title = {{Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {5:1--5:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.5},
URN = {urn:nbn:de:0030-drops-204732},
doi = {10.4230/OASIcs.WCET.2024.5},
annote = {Keywords: Bandwidth Regulation, System-on-Chip, FPGA}
}
Document
Invited Paper
Invited Paper: Statistical, Stochastic or Probabilistic (Worst-Case Execution) Execution Time? - What Impact on the Multicore Composability
Abstract
The problem of estimating worst-case execution times of programs on processors has appeared within the context of critical industries like avionics or space. Rapidly adopted by the real-time scheduling community, worst-case execution time estimates of programs or tasks are mandatory to understand the time behaviour of a real-time system. Analyzing such time behaviour is done, often, with an important pessimism due to the consideration of worst-case scenarios. A decreased pessimism has been obtained by understanding that large execution times of a program have low probability of appearance. Probabilistic (worst-case) execution time notion has been proposed. Nevertheless, independence hypotheses makes difficult today to calculate the probabilistic worst-case execution time of a program and current approaches are built, often, on statistical estimators based on the use of Extreme Value Theory or concentration inequalities. Thus, future probabilistic time analyses are expected to consider worst-case execution times estimates obtained by using statistical estimators on measured execution times instead of probabilistic (worst-case) execution times estimations. Within this paper, we discuss the opportunity of differentiating probabilistic (worst-case) execution times from statistical (worst-case) execution times and how dependence between execution times are better or easier captured by each of the definition, while stochastic execution times could be, also, an appropriate alternative.
Cite as
Liliana Cucu-Grosjean. Invited Paper: Statistical, Stochastic or Probabilistic (Worst-Case Execution) Execution Time? - What Impact on the Multicore Composability. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 6:1-6:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{cucugrosjean:OASIcs.WCET.2024.6,
author = {Cucu-Grosjean, Liliana},
title = {{Invited Paper: Statistical, Stochastic or Probabilistic (Worst-Case Execution) Execution Time? - What Impact on the Multicore Composability}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {6:1--6:10},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.6},
URN = {urn:nbn:de:0030-drops-204746},
doi = {10.4230/OASIcs.WCET.2024.6},
annote = {Keywords: Worst-case execution time, probabilistic analyses, statistical estimator}
}
Document
Invited Talk
Machine Learning for Timing Analysis: The Good, the Bad and the Ugly (Invited Talk)
Abstract
The microarchitecture of processors is becoming increasingly complex and less documented, making the design of timing models for WCET calculation increasingly complicated, if not impossible. We have recently experimented with the use of machine learning techniques (ML) to predict the WCET of basic blocks [Amalou et al., 2021; Abderaouf N. Amalou et al., 2022; Amalou et al., 2023; Abderaouf Nassim Amalou, 2023; Abderaouf Nassim Amalou et al., 2024]. Predicted WCETs can then be integrated into static WCET calculation tools, resulting in a hybrid WCET calculation.
In this keynote, we present our experience using ML for WCET calculation, across a range of architectures, from very simple ones (MSP430, Cortex M4) to more complex architectures. Rather than presenting only what worked, we also discuss in this keynote the bad, and even very bad, surprises encountered during the process, and how we overcame (most of) them.
Cite as
Isabelle Puaut. Machine Learning for Timing Analysis: The Good, the Bad and the Ugly (Invited Talk). In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, p. 7:1, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{puaut:OASIcs.WCET.2024.7,
author = {Puaut, Isabelle},
title = {{Machine Learning for Timing Analysis: The Good, the Bad and the Ugly}},
booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
pages = {7:1--7:1},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-346-1},
ISSN = {2190-6807},
year = {2024},
volume = {121},
editor = {Carle, Thomas},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.7},
URN = {urn:nbn:de:0030-drops-204753},
doi = {10.4230/OASIcs.WCET.2024.7},
annote = {Keywords: Worst-Case Execution Time (WCET) estimation, Machine Learning, Explainable ML models}
}