Machine Learning for Timing Analysis: The Good, the Bad and the Ugly (Invited Talk)

Abstract

The microarchitecture of processors is becoming increasingly complex and less documented, making the design of timing models for WCET calculation increasingly complicated, if not impossible. We have recently experimented with the use of machine learning techniques (ML) to predict the WCET of basic blocks [Amalou et al., 2021; Abderaouf N. Amalou et al., 2022; Amalou et al., 2023; Abderaouf Nassim Amalou, 2023; Abderaouf Nassim Amalou et al., 2024]. Predicted WCETs can then be integrated into static WCET calculation tools, resulting in a hybrid WCET calculation. 
In this keynote, we present our experience using ML for WCET calculation, across a range of architectures, from very simple ones (MSP430, Cortex M4) to more complex architectures. Rather than presenting only what worked, we also discuss in this keynote the bad, and even very bad, surprises encountered during the process, and how we overcame (most of) them.