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Drechsler, Rolf ; Eggersglüß, Stephan ; Fey, Görschwin ; Tille, Daniel

SAT-based Automatic Test Pattern Generation

08351.DrechslerRolf.Paper.2015.pdf (0.08 MB)


Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformation, relevant information about the problem might get lost and therefore is not available in the solving process.

In the following we briefly motivate the problem and provide the latest developments in the field. The technique was implemented and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. Significant improvements in overall performance and
robustness are demonstrated.

BibTeX - Entry

  author =	{Rolf Drechsler and Stephan Eggersgl{\"u}{\"s} and G{\"o}rschwin Fey and Daniel Tille},
  title =	{SAT-based Automatic Test Pattern Generation},
  booktitle =	{Evolutionary Test Generation},
  year =	{2009},
  editor =	{Holger Schlingloff and Tanja E. J. Vos and Joachim Wegener},
  number =	{08351},
  series =	{Dagstuhl Seminar Proceedings},
  ISSN =	{1862-4405},
  publisher =	{Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany},
  address =	{Dagstuhl, Germany},
  URL =		{},
  annote =	{Keywords: Circuit, ATPG, SAT, Boolean Satisfiability}

Keywords: Circuit, ATPG, SAT, Boolean Satisfiability
Collection: 08351 - Evolutionary Test Generation
Issue Date: 2009
Date of publication: 25.05.2009

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