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Alves de Barros-Naviner, Lirida ; Naviner, Jean-François ; Teixeira Franco, Denis ; Correia de Vasconcelos, Mai

Methods and Metrics for Reliability Assessment

08371.NavinerLirida.Paper.1925.pdf (0.5 MB)


This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits.We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection schemes.

BibTeX - Entry

  author =	{Lirida Alves de Barros-Naviner and Jean-Fran{\c{c}}ois Naviner and Denis Teixeira Franco and Mai Correia de Vasconcelos},
  title =	{Methods and Metrics for Reliability Assessment},
  booktitle =	{Fault-Tolerant Distributed Algorithms on VLSI Chips },
  year =	{2009},
  editor =	{Bernadette Charron-Bost and Shlomi Dolev and Jo Ebergen and Ulrich Schmid},
  number =	{08371},
  series =	{Dagstuhl Seminar Proceedings},
  ISSN =	{1862-4405},
  publisher =	{Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany},
  address =	{Dagstuhl, Germany},
  URL =		{},
  annote =	{Keywords: Reliability, fault tolerance, combinational logic}

Keywords: Reliability, fault tolerance, combinational logic
Seminar: 08371 - Fault-Tolerant Distributed Algorithms on VLSI Chips
Issue Date: 2009
Date of publication: 13.03.2009

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