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DOI: 10.4230/OASIcs.WCET.2009.2288
URN: urn:nbn:de:0030-drops-22885
URL: http://drops.dagstuhl.de/opus/volltexte/2009/2288/
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Schoeberl, Martin ; Puschner, Peter

Is Chip-Multiprocessing the End of Real-Time Scheduling?

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Abstract

Chip-multiprocessing is considered the future path for performance enhancements in computer architecture. Eight processor cores on a single chip are state-of-the art and several hundreds of cores on a single die are expected in the near future. General purpose computing is facing the challenge how to use the many cores. However, in embedded real-time systems thread-level parallelism is naturally used. In this paper we assume a system where we can dedicate a single core for each thread. In that case classic real-time scheduling disappears. However, the threads, running on their dedicated core, still compete for a shared resource, the main memory. A time-sliced memory arbiter is used to avoid timing influences between threads. The schedule of the arbiter is integrated into the worst-case execution time (WCET) analysis. The WCET results are used as a feedback to regenerate the arbiter schedule. Therefore, we schedule memory access instead of CPU time.

BibTeX - Entry

@InProceedings{schoeberl_et_al:OASIcs:2009:2288,
  author =	{Martin Schoeberl and Peter Puschner},
  title =	{{Is Chip-Multiprocessing the End of Real-Time Scheduling?}},
  booktitle =	{9th International Workshop on Worst-Case Execution Time Analysis (WCET'09) },
  pages =	{1--11},
  series =	{OpenAccess Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-14-9},
  ISSN =	{2190-6807},
  year =	{2009},
  volume =	{10},
  editor =	{Niklas Holsti},
  publisher =	{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2009/2288},
  URN =		{urn:nbn:de:0030-drops-22885},
  doi =		{http://dx.doi.org/10.4230/OASIcs.WCET.2009.2288},
  note =	{also published in print by Austrian Computer Society (OCG) with ISBN 978-3-85403-252-6},
  annote =	{Keywords: WCET analysis, multicore, chip multiprocessing, memory access scheduling}
}

Keywords: WCET analysis, multicore, chip multiprocessing, memory access scheduling
Seminar: 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09)
Issue Date: 2009
Date of publication: 26.11.2009


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