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URN: urn:nbn:de:0030-drops-28389
URL: http://drops.dagstuhl.de/opus/volltexte/2010/2838/
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Huthmann, Jens ;
Müller, Peter ;
Stock, Florian ;
Hildenbrand, Dietmar ;
Koch, Andreas
Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators
Abstract
Geometric Algebra (GA), a generalization of quaternions and complex numbers, is a very
powerful framework for intuitively expressing and manipulating the complex
geometric relationships common to engineering problems.
However, actual processing of GA expressions is very compute intensive, and
acceleration is generally required for practical use. GPUs and FPGAs offer
such acceleration, while requiring only low-power per operation.
In this paper, we present key components of a proof-of-concept compile flow
combining symbolic and hardware optimization techniques to
automatically generate hardware accelerators from the abstract GA descriptions that are suitable for high-performance embedded computing.
BibTeX - Entry
@InProceedings{huthmann_et_al:DSP:2010:2838,
author = {Jens Huthmann and Peter M{\"u}ller and Florian Stock and Dietmar Hildenbrand and Andreas Koch},
title = {{Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators}},
booktitle = {Dynamically Reconfigurable Architectures},
year = {2010},
editor = {Peter M. Athanas and J{\"u}rgen Becker and J{\"u}rgen Teich and Ingrid Verbauwhede},
number = {10281},
series = {Dagstuhl Seminar Proceedings},
ISSN = {1862-4405},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany},
address = {Dagstuhl, Germany},
URL = {http://drops.dagstuhl.de/opus/volltexte/2010/2838},
annote = {Keywords: Geometric Algebra FPGA High-Level-Compiler Gaalop}
}
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Keywords: |
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Geometric Algebra FPGA High-Level-Compiler Gaalop |
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Seminar: |
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10281 - Dynamically Reconfigurable Architectures |
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Issue Date: |
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2010 |
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Date of publication: |
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14.12.2010 |
