Traces as a Solution to Pessimism and Modeling Costs in WCET Analysis

Abstract

WCET analysis models for superscalar out-of-order CPUs 
    generally need to be pessimistic in order to account for
    a wide range of possible dynamic behavior. CPU hardware modifications 
    could be used to constrain operations to known execution paths
    called traces, permitting exploitation of instruction 
    level parallelism with guaranteed
    timing. Previous implementations of traces have used
    microcode to constrain operations, but other possibilities
    exist. A new implementation strategy (virtual 
    traces) is introduced here.

In this paper the benefits and costs of traces are discussed.
    Advantages of traces include a reduction in pessimism in WCET analysis,
    with the need to accurately model CPU internals removed. Disadvantages
    of traces include a reduction of peak throughput of the CPU, a need
    for deterministic memory and a potential increase in the complexity
    of WCET models.