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DOI: 10.4230/OASIcs.WCET.2008.1666
URN: urn:nbn:de:0030-drops-16666
URL: http://drops.dagstuhl.de/opus/volltexte/2008/1666/
Whitham, Jack ; Audsley, Neil

Traces as a Solution to Pessimism and Modeling Costs in WCET Analysis

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Abstract

WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modifications could be used to constrain operations to known execution paths called traces, permitting exploitation of instruction level parallelism with guaranteed timing. Previous implementations of traces have used microcode to constrain operations, but other possibilities exist. A new implementation strategy (virtual traces) is introduced here. In this paper the benefits and costs of traces are discussed. Advantages of traces include a reduction in pessimism in WCET analysis, with the need to accurately model CPU internals removed. Disadvantages of traces include a reduction of peak throughput of the CPU, a need for deterministic memory and a potential increase in the complexity of WCET models.

BibTeX - Entry

@InProceedings{whitham_et_al:DSP:2008:1666,
  author =	{Jack Whitham and Neil Audsley},
  title =	{Traces as a Solution to Pessimism and Modeling Costs in WCET Analysis},
  booktitle =	{8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis},
  year =	{2008},
  editor =	{Raimund Kirner},
  publisher =	{Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany},
  address =	{Dagstuhl, Germany},
  URL =		{http://drops.dagstuhl.de/opus/volltexte/2008/1666},
  annote =	{Keywords: WCET superscalar cpu virtual traces},
  ISBN =	{978-3-939897-10-1},
  note=		{also published in print by Austrian Computer Society (OCG) under ISBN 978-3-85403-237-3}
}

Keywords: WCET superscalar cpu virtual traces
Seminar: 8th International Workshop on Worst-Case Execution Time WCET Analysis (WCET'08)
Documenttype: InProceedings
Issue date: 2008
Date of publication: 13.11.2008

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