@Article{sensfelder_et_al:DARTS.5.1.7,
author = {Sensfelder, Nathana\"{e}l and Brunel, Julien and Pagetti, Claire},
title = {{Modeling Cache Coherence to Expose Interference}},
pages = {7:1--7:2},
journal = {Dagstuhl Artifacts Series},
ISSN = {2509-8195},
year = {2019},
volume = {5},
number = {1},
editor = {Sensfelder, Nathana\"{e}l and Brunel, Julien and Pagetti, Claire},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/DARTS.5.1.7},
URN = {urn:nbn:de:0030-drops-107358},
doi = {10.4230/DARTS.5.1.7},
annote = {Keywords: Real-time systems, multi-core processor, cache coherence, formal methods}
}