Modeling Cache Coherence to Expose Interference (Artifact)

Authors Nathanaël Sensfelder, Julien Brunel, Claire Pagetti

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  • Filesize: 275 kB
  • 2 pages

Document Identifiers

Author Details

Nathanaël Sensfelder
  • ONERA, Toulouse, France
Julien Brunel
  • ONERA, Toulouse, France
Claire Pagetti
  • ONERA, Toulouse, France


We would like to thank Mamoun Filali-Amine (IRIT-CNRS) for his helpful insights on how to validate our model.

Cite AsGet BibTex

Nathanaël Sensfelder, Julien Brunel, and Claire Pagetti. Modeling Cache Coherence to Expose Interference (Artifact). In Special Issue of the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Dagstuhl Artifacts Series (DARTS), Volume 5, Issue 1, pp. 7:1-7:2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)



To facilitate programming, most multi-core processors feature automated mechanisms maintaining coherence between each core’s cache. These mechanisms introduce interference, that is, delays caused by concurrent access to a shared resource. This type of interference is hard to predict, leading to the mechanisms being shunned by real-time system designers, at the cost of potential benefits in both running time and system complexity. We believe that formal methods can provide the means to ensure that the effects of this interference are properly exposed and mitigated. Consequently, we propose a nascent framework relying on timed automata to model and analyze the interference caused by cache coherence.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Multicore architectures
  • Computer systems organization → Real-time systems
  • Real-time systems
  • multi-core processor
  • cache coherence
  • formal methods


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