This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits.We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection schemes.
@InProceedings{alvesdebarrosnaviner_et_al:DagSemProc.08371.5, author = {Alves de Barros-Naviner, Lirida and Naviner, Jean-Fran\c{c}ois and Teixeira Franco, Denis and Correia de Vasconcelos, Mai}, title = {{Methods and Metrics for Reliability Assessment}}, booktitle = {Fault-Tolerant Distributed Algorithms on VLSI Chips}, pages = {1--15}, series = {Dagstuhl Seminar Proceedings (DagSemProc)}, ISSN = {1862-4405}, year = {2009}, volume = {8371}, editor = {Bernadette Charron-Bost and Shlomi Dolev and Jo Ebergen and Ulrich Schmid}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.08371.5}, URN = {urn:nbn:de:0030-drops-19252}, doi = {10.4230/DagSemProc.08371.5}, annote = {Keywords: Reliability, fault tolerance, combinational logic} }
Feedback for Dagstuhl Publishing