10281 Summary – Dynamically Reconfigurable Architectures

Authors Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede

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Peter M. Athanas
Jürgen Becker
Jürgen Teich
Ingrid Verbauwhede

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Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede. 10281 Summary – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)


Dynamic and partial reconfiguration of hardware architectures such as FPGAs and coarse grain processing arrays bring an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. When compared to emerging software-programmable Multi-Processor System-on-a-Chip (MPSoC) solutions, they benefit a lot from lower cost, more dedication and fit to a certain problem class as well as power and area efficiency. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity.
  • Dynamically Run-Time Reconfigurable Computing Architectures
  • Self- adaptive Systems
  • Computational Models
  • Circuit Technologies
  • System Architecture
  • CAD Tool Support
  • Reconfigurable/Adaptive Computing based on Nanotechnologies


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