Design and Implementation of an Object-Oriented DPR-Framework

Nowadays, two innovative future trends regarding hardware development and hardware description can be found. The first trend concerns the hardware itself. Modern Xilinx FPGAs provide the possibility to be reconfigured partially and dynamically - which is called dynamical partial reconfiguration (DPR). DPR opens a huge field of new functionalities on FPGAs. However, using DPR means struggling with architectural details of the used FPGAs and the according synthesis and implementation tools. A developer would focus most of the time on DPR and only a small part of the time on the implementation of the actual modules - of course that is the opposite of what hardware engineers want to do. The second trend concerns the way hardware is described. Many hardware developing groups are looking forward to an HDL which operates on the algorithmic level, since this would come with a significant increase in productivity. The aim is to be able to translate common software algorithms to hardware in an efficient way (which is called high-level synthesis or HLS). Although both DPR and HLS are important future trends regarding hardware design, they develop quite independently. Today's software-to-hardware compilers focus on conventional hardware and therefore have to remove dynamic aspects such as the instantiation of calculating modules at runtime. Even object-oriented languages like SystemC do not support the dynamic instantiation of objects (that means the usage of new or delete outside of the constructor) for synthesis at all. On the other hand, DPR tools are working on the lowest possible layer regarding FPGAs: the bitfile level. Our research focuses on the design and the implementation of a Framework combining the two technologies, since this has the potential to kill two birds with one stone. Firstly, DPR can change the programming paradigm in future HDLs regarding dynamic instantiations. Dynamic parts would not have to be removed any longer but could be realized on the target FPGA using DPR. Secondly, a high-level language support of DPR technologies could help end its shadowy existence and turn it into a commonly used method.