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HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems

Authors Pedro Benedicte , Carles Hernandez , Jaume Abella , Francisco J. Cazorla



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Pedro Benedicte
  • Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Barcelona, Spain
Carles Hernandez
  • Barcelona Supercomputing Center, Barcelona, Spain
Jaume Abella
  • Barcelona Supercomputing Center, Barcelona, Spain
Francisco J. Cazorla
  • Barcelona Supercomputing Center and IIIA-CSIC, Barcelona, Spain

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Pedro Benedicte, Carles Hernandez, Jaume Abella, and Francisco J. Cazorla. HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Leibniz International Proceedings in Informatics (LIPIcs), Volume 106, pp. 3:1-3:22, Schloss Dagstuhl - Leibniz-Zentrum für Informatik (2018)
https://doi.org/10.4230/LIPIcs.ECRTS.2018.3

Abstract

High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and automotive already featuring two or more cache levels. One of the most critical elements for MLC is the write policy that not only affects several key metrics such as performance, WCET estimates, energy/power, and reliability, but also the design of complexity-prone cache coherence protocol and cache reliability solutions. In this paper we make an extensive analysis of existing write policies, namely write-through (WT) and write-back (WB). In the context of the real-time domain, we show that no write policy is superior for all metrics: WT simplifies the design of the coherence and reliability solutions at the cost of performance, WCET, and energy; while WB improves performance and energy results, but complicates cache design. To take the best of each policy, we propose Hybrid Write Policy (HWP) a low-complexity hardware mechanism that reconciles the benefits of WT in terms of simplifying the cache design (e.g. coherence solution) and the benefits of WB in improved average performance and WCET estimates as the pressure on the interconnection network increases. Guaranteed performance results show that HWP scales with core count similar to WB. Likewise, HWP reduces cache energy usage of WT, to levels similar to those of WB. These benefits are obtained while retaining the reduced coherence complexity of WT, in contrast to high coherence costs under WB.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Parallel architectures
  • Computer systems organization → Embedded systems
  • Computer systems organization → Real-time systems
  • Computer systems organization → Dependable and fault-tolerant systems and networks
Keywords
  • multilevel caches
  • real-time systems
  • multicores
  • WCET

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