Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study

Authors Xavier Palomo, Mikel Fernandez, Sylvain Girbal, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Laurent Rioux



PDF
Thumbnail PDF

File

LIPIcs.ECRTS.2020.15.pdf
  • Filesize: 0.92 MB
  • 25 pages

Document Identifiers

Author Details

Xavier Palomo
  • Barcelona Supercomputing Center, Spain
Mikel Fernandez
  • Barcelona Supercomputing Center, Spain
Sylvain Girbal
  • Thales Research, Palaiseau, France
Enrico Mezzetti
  • Barcelona Supercomputing Center, Spain
Jaume Abella
  • Barcelona Supercomputing Center, Spain
Francisco J. Cazorla
  • Barcelona Supercomputing Center, Spain
Laurent Rioux
  • Thales Research, Palaiseau, France

Cite AsGet BibTex

Xavier Palomo, Mikel Fernandez, Sylvain Girbal, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, and Laurent Rioux. Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Leibniz International Proceedings in Informatics (LIPIcs), Volume 165, pp. 15:1-15:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)
https://doi.org/10.4230/LIPIcs.ECRTS.2020.15

Abstract

The demand for increased computing performance is driving industry in critical-embedded systems (CES) domains, e.g. space, towards the use of multicores processors. Multicores, however, pose several challenges that must be addressed before their safe adoption in critical embedded domains. One of the prominent challenges is software timing analysis, a fundamental step in the verification and validation process. Monitoring and profiling solutions, traditionally used for debugging and optimization, are increasingly exploited for software timing in multicores. In particular, hardware event monitors related to requests to shared hardware resources are building block to assess and restraining multicore interference. Modern timing analysis techniques build on event monitors to track and control the contention tasks can generate each other in a multicore platform. In this paper we look into the hardware profiling problem from an industrial perspective and address both methodological and practical problems when monitoring a multicore application. We assess pros and cons of several profiling and tracing solutions, showing that several aspects need to be taken into account while considering the appropriate mechanism to collect and extract the profiling information from a multicore COTS platform. We address the profiling problem on a representative COTS platform for the aerospace domain to find that the availability of directly-accessible hardware counters is not a given, and it may be necessary to the develop specific tools that capture the needs of both the user’s and the timing analysis technique requirements. We report challenges in developing an event monitor tracing tool that works for bare-metal and RTEMS configurations and show the accuracy of the developed tool-set in profiling a real aerospace application. We also show how the profiling tools can be exploited, together with handcrafted benchmarks, to characterize the application behavior in terms of multicore timing interference.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Multicore architectures
Keywords
  • Multicore Contention
  • Timing interference
  • Hardware Event Counters
  • PMC

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads

References

  1. Jaume Abella, Carles Hernández, Eduardo Qui~nones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Pérez, Enrico Mezzetti, and Tullio Vardanega. WCET analysis methods: Pitfalls and challenges on their trustworthiness. In 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015, Siegen, Germany, June 8-10, 2015, pages 39-48. IEEE, 2015. URL: https://doi.org/10.1109/SIES.2015.7185039.
  2. ARM. ARM® CoreSight©ip. URL: https://www.arm.com/products/system-ip/coresight-debug-trace.
  3. ARM. ARM Advanced Microcontroller Bus Architecture (AMBA) 5 AMBA High-performance Bus (AHB) Protocol Specification, 2015. Google Scholar
  4. Thomas G. Baker. Lessons learned integrating COTS into systems. In John C. Dean and Andrée Gravel, editors, COTS-Based Software Systems, First International Conference, ICCBSS 2002, Orlando, FL, USA, February 4-6, 2002, Proceedings, volume 2255 of Lecture Notes in Computer Science, pages 21-30. Springer, 2002. URL: https://doi.org/10.1007/3-540-45588-4_3.
  5. Adam Betts, Nicholas Merriam, and Guillem Bernat. Hybrid measurement-based WCET analysis at the source level using object-level traces. In Björn Lisper, editor, 10th International Workshop on Worst-Case Execution Time Analysis, WCET 2010, July 6, 2010, Brussels, Belgium, volume 15 of OASICS, pages 54-63. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, 2010. URL: https://doi.org/10.4230/OASIcs.WCET.2010.54.
  6. Jingyi Bin, Sylvain Girbal, Daniel Gracia Pérez, Arnaud Grasset, and Alain Mérigot. Studying co-running avionic real-time applications on multi-core COTS architectures. In Embedded Real Time Software and Systems (ERTS2014), Toulouse, France, February 2014. URL: https://hal.archives-ouvertes.fr/hal-02271379.
  7. Shirley Browne, Jack J. Dongarra, Nathan Garner, George Ho, and Philip Mucci. A portable programming interface for performance evaluation on modern processors. Int. J. High Perform. Comput. Appl., 14(3):189-204, 2000. URL: https://doi.org/10.1177/109434200001400303.
  8. Dakshina Dasari and Vincent Nélis. An analysis of the impact of bus contention on the WCET in multicores. In Geyong Min, Jia Hu, Lei (Chris) Liu, Laurence Tianruo Yang, Seetharami Seelam, and Laurent Lefèvre, editors, 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, HPCC-ICESS 2012, Liverpool, United Kingdom, June 25-27, 2012, pages 1450-1457. IEEE Computer Society, 2012. URL: https://doi.org/10.1109/HPCC.2012.212.
  9. Olivier Notebaert (Airbus Defence and Space). On-board software technology trends in space applications (keynote). In Euromicro Conference on Real-Time Systems, ECRTS'2018, 2018. Google Scholar
  10. Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-Askasua, Tullio Vardanega, and Francisco J. Cazorla. Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. In Martin Schoeberl, editor, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), volume 55 of OpenAccess Series in Informatics (OASIcs), pages 1:1-1:11, Dagstuhl, Germany, 2016. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. URL: https://doi.org/10.4230/OASIcs.WCET.2016.1.
  11. Enrique Díaz, Mikel Fernández, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, and Francisco J. Cazorla. MC2: multicore and cache analysis via deterministic and probabilistic jitter bounding. In Reliable Software Technologies - Ada-Europe 2017 - 22nd Ada-Europe International Conference on Reliable Software Technologies, Vienna, Austria, June 12-16, 2017, Proceedings, pages 102-118, 2017. URL: https://doi.org/10.1007/978-3-319-60588-3_7.
  12. Enrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, and Francisco J. Cazorla. Modelling multicore contention on the aurix^tm tc27x. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pages 97:1-97:6, 2018. URL: https://doi.org/10.1145/3195970.3196077.
  13. Boris Dreyer, Christian Hochberger, Alexander Lange, Simon Wegener, and Alexander Weiss. Continuous non-intrusive hybrid WCET estimation using waypoint graphs. In Martin Schoeberl, editor, 16th International Workshop on Worst-Case Execution Time Analysis, WCET 2016, July 5, 2016, Toulouse, France, volume 55 of OASICS, pages 4:1-4:11. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016. URL: https://doi.org/10.4230/OASIcs.WCET.2016.4.
  14. Boris Dreyer, Christian Hochberger, Simon Wegener, and Alexander Weiss. Precise continuous non-intrusive measurement-based execution time estimation. In Francisco J. Cazorla, editor, 15th International Workshop on Worst-Case Execution Time Analysis, WCET 2015, July 7, 2015, Lund, Sweden, volume 47 of OASICS, pages 45-54. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2015. URL: https://doi.org/10.4230/OASIcs.WCET.2015.45.
  15. European Aviation Safety Agency. The Use of Multicore Processors in Airborne Systems (MULCORS). Technical Report EASA/2011/6, European Aviation Safety Agency, 2011. Google Scholar
  16. European Cooperation for Space Standardization. Standard ECSS-E-40: Space Software: Engineering. Technical report, European Cooperation for Space Standardization, 2013. Google Scholar
  17. Federal Aviation Administration, Certification Authorities Software Team (CAST). CAST-32A Multi-core Processors, 2016. Google Scholar
  18. Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Qui~nones, Tullio Vardanega, and Francisco J. Cazorla. Resource usage templates and signatures for COTS multicore processors. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, pages 155:1-155:6. ACM, 2015. URL: https://doi.org/10.1145/2744769.2744901.
  19. Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Qui~nones, Tullio Vardanega, and Francisco J. Cazorla. Computing safe contention bounds for multicore resources with round-robin and FIFO arbitration. IEEE Trans. Computers, 66(4):586-600, 2017. URL: https://doi.org/10.1109/TC.2016.2616307.
  20. Nexus 5001 Forum. Nexus 5001 forum. URL: http://www.nexus5001.org.
  21. Jeremy Giesen, Pedro Benedicte, Enrico Mezzetti, Jaume Abella, and Francisco J. Cazorla. Modeling contention interference in crossbar-based systems via sequence-aware pairing (SeAP). In 26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020, Sydney, Australia, April 21-24, 2020, 2020. Google Scholar
  22. Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Enrique Fernández, and Francisco J. Cazorla. ePAPI: Performance Application Programming Interface for Embedded Platforms. In Sebastian Altmeyer, editor, 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019), volume 72 of OpenAccess Series in Informatics (OASIcs), pages 3:1-3:13, Dagstuhl, Germany, 2019. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. URL: https://doi.org/10.4230/OASIcs.WCET.2019.3.
  23. Sylvain Girbal, Xavier Jean, Jimmy Le Rhun, Daniel Gracia Pérez, and Marc Gatti. Deterministic Platform Software for hard real-time systems using multi-core COTS. In Proceedings of the 34th Digital Avionics Systems Conference, DASC'2015, 2015. URL: https://doi.org/10.1109/DASC.2015.7311646.
  24. Sylvain Girbal, Daniel Gracia Pérez, Jimmy Le Rhun, Madeleine Faugère, Claire Pagetti, and Guy Durrieu. A complete toolchain for an interference-free deployment of avionic applications on multi-core systems. In Proceedings of the 34th Digital Avionics Systems Conference, DASC'2015, 2015. URL: https://doi.org/10.1109/DASC.2015.7311625.
  25. GLIWA GmbH. T1.timing. URL: https://www.gliwa.com/.
  26. Reinhold Heckmann and Christian Ferdinand. Verifying safety-critical timing and memory-usage properties of embedded software by abstract interpretation. In Proceedings of the conference on Design, Automation and Test in Europe, DATE'05, pages 618-619, 2005. URL: https://doi.org/10.1109/DATE.2005.326.
  27. Rafia Inam, Mikael Sjödin, and Marcus Jägemar. Bandwidth measurement using performance counters for predictable multicore software. In Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, ETFA 2012, Krakow, Poland, September 17-21, 2012, pages 1-4, 2012. URL: https://doi.org/10.1109/ETFA.2012.6489714.
  28. International Electrotechnical Commission. IEC 61508: Functional safety of electrical, electronic, or programmable electronic safety-related systems. Technical report, International Electrotechnical Commission, 2011. Google Scholar
  29. International Organization for Standardization. ISO/DIS 26262. Road Vehicles - Functional Safety, 2009. Google Scholar
  30. Daniel Kästner, Markus Pister, Simon Wegener, and Christian Ferdinand. TimeWeaver: A Tool for Hybrid Worst-Case Execution Time Analysis. In Sebastian Altmeyer, editor, 19th International Workshop on Worst-Case Execution Time Analysis (WCET 2019), volume 72 of OpenAccess Series in Informatics (OASIcs), pages 1:1-1:11, Dagstuhl, Germany, 2019. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. URL: https://doi.org/10.4230/OASIcs.WCET.2019.1.
  31. Raimund Kirner and Peter Puschner. Obstacles in worst-case execution time analysis. In Proceedings of the 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing, pages 333-339, 2008. URL: https://doi.org/10.1109/ISORC.2008.65.
  32. Linux. perf: Linux profiling with performance counters. URL: https://perf.wiki.kernel.org/index.php/Main_Page.
  33. Rapita Trace Box (RTBx) Data Logger). https://www.rapitasystems.com/products/rtbx, 2020. URL: https://www.rapitasystems.com/products/rtbx.
  34. Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, and Francisco J. Cazorla. High-integrity performance monitoring units in automotive chips for reliable timing V&V. IEEE Micro, 38(1):56-65, 2018. URL: https://doi.org/10.23919/DATE.2019.8715177.
  35. Enrico Mezzetti and Tullio Vardanega. On the industrial fitness of wcet analysis. 11th International Workshop on Worst-Case Execution-Time Analysis, 2011. URL: https://doi.org/10.1109/sies.2015.7185039.
  36. Jan Nowotsch and Michael Paulitsch. Leveraging multi-core computing architectures in avionics. In Cristian Constantinescu and Miguel P. Correia, editors, 2012 Ninth European Dependable Computing Conference, Sibiu, Romania, May 8-11, 2012, pages 132-143. IEEE Computer Society, 2012. URL: https://doi.org/10.1109/EDCC.2012.27.
  37. Jan Nowotsch, Michael Paulitsch, Daniel Buhler, Henrik Theiling, Simon Wegener, and Michael Schmidt. Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In 26th Euromicro Conference on Real-Time Systems, ECRTS 2014, Madrid, Spain, July 8-11, 2014, pages 109-118. IEEE Computer Society, 2014. URL: https://doi.org/10.1109/ECRTS.2014.20.
  38. Rajendra Patel and Arvind Rajawat. A survey of embedded software profiling methodologies. CoRR, abs/1312.2949, 2013. URL: http://arxiv.org/abs/1312.2949.
  39. Peter P. Puschner and Alan Burns. Guest editorial: A review of worst-case execution-time analysis. Real-Time Systems, 18(2/3):115-128, 2000. URL: https://doi.org/10.1023/A:1008119029962.
  40. Radio Technical Commission for Aeronautics (RTCA) and EURopean Organisation for Civil Aviation Equipment (EUROCAE). DO-297: Software, electronic, integrated modular avionics (IMA) development guidance and certification considerations. Technical report, EUROCAE, 2005. Google Scholar
  41. Petar Radojković et al. On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. ACM TACO, 2012. Google Scholar
  42. Jan Reineke. Challenges for timing analysis of multi-core architectures. Workshop on Foundational and Practical Aspects of Resource Analysis, 2017. Invited Talk. Google Scholar
  43. Rapita Verification Suite (RVS). https://www.rapitasystems.com/, 2020. URL: https://www.rapitasystems.com/.
  44. Karsten Schmidt, Denny Marx, Jens Harnisch, Albrecht Mayer, Udo Dannebaum, and Herbert Christlbauer. Non-intrusive tracing at first instruction. In SAE Technical Paper. SAE International, April 2015. URL: https://doi.org/10.4271/2015-01-0176.
  45. Jason G. Tong and Mohammed A. S. Khalid. Profiling tools for fpga-based embedded systems: Survey and quantitative comparison. JCP, 3(6):1-14, 2008. URL: https://doi.org/10.4304/jcp.3.6.1-14.
  46. https://www.gaisler.com/doc/gr712rc-usermanual.pdf. GR712RC User Manual. Cobham Gaisler. URL: https://www.gaisler.com/doc/gr712rc-usermanual.pdf.
  47. https://www.gaisler.com/doc/grmon2.pdf. GRMON2 User’s Manual. Cobham Gaisler. URL: https://www.gaisler.com/doc/grmon2.pdf.
  48. Vector Informatik GmbH. TA Tool Suite. URL: https://www.timing-architects.com/.
  49. Reinhard Wilhelm. Mixed feelings about mixed criticality (invited paper). In Florian Brandner, editor, 18th International Workshop on Worst-Case Execution Time Analysis, WCET 2018, July 3, 2018, Barcelona, Spain, volume 63 of OASICS, pages 1:1-1:9. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018. URL: https://doi.org/10.4230/OASIcs.WCET.2018.1.
  50. Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David B. Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter P. Puschner, Jan Staschulat, and Per Stenström. The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embedded Comput. Syst., 7(3):36:1-36:53, 2008. URL: https://doi.org/10.1145/1347375.1347389.
  51. Reinhard Wilhelm and Jan Reineke. Embedded systems: Many cores — many problems. In 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), pages 176-180, June 2012. URL: https://doi.org/10.1109/SIES.2012.6356583.
  52. Wilhelm R. et al. The worst-case execution-time problem overview of methods and survey of tools. ACM Transactions on Embedded Computing Systems, 7:1-53, May 2008. Google Scholar
  53. Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha. Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In 19th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2013, Philadelphia, PA, USA, April 9-11, 2013, pages 55-64, 2013. URL: https://doi.org/10.1109/RTAS.2013.6531079.
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail