HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper)

Authors Mohammadhassan Gholami Derouei , Paolo Valente , Marco Solieri , Andrea Marongiu

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Mohammadhassan Gholami Derouei
  • Università degli Studi di Modena e Reggio Emilia, Italy
  • Minerva Systems srl, Modena, Italy
Paolo Valente
  • Università degli Studi di Modena e Reggio Emilia, Italy
Marco Solieri
  • Minerva Systems srl, Modena, Italy
Andrea Marongiu
  • Università degli Studi di Modena e Reggio Emilia, Italy


Authors are grateful to Tomasz Kloda at TUM, and Benjamin Rouxel at UNIMORE, with whom they enjoyed inspiring discussions in the conception of this work.

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Mohammadhassan Gholami Derouei, Paolo Valente, Marco Solieri, and Andrea Marongiu. HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 1:1-1:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


Current homogeneous and heterogeneous computing systems reach high performance through parallelization. Yet, parallel execution of tasks entails non-trivial latency-vs-throughput issues when it comes to concurrent accesses to shared memory. In this respect, effective bandwidth regulation solutions do exist, and provide a basic mechanism to control the latency of memory accesses. Such solutions, though, are often cumbersome to deploy and to configure to guarantee both bounded latency and high utilization of the memory bandwidth. The problem is that memory latency varies non-linearly with the number and type of concurrent accesses, and the latter may in turn vary with time, often unpredictably. For this reason, previous attempts at memory regulation in scheduling solutions resulted either in poor real-time execution guarantees, or in severe underutilization of the memory bandwidth. In this paper, we outline High Memory Bandwidth (HMB), a scheduling solution that guarantees bounded response times to real-time task sets through memory regulation, while also reaching a high utilization memory bandwidth. Since the complete solution is complex, just like the problem it addresses, this preliminary work defines in full detail only the core mechanism. This mechanism builds on the notion of memory access slowdown experienced by any processor performing back-to-back memory operations; this slowdown is due to the interference generated by other processors also accessing the memory at the same time. The core mechanism assumes that each processor can tolerate a certain amount of slowdown before the timing behavior of the task(s) it is running is compromised. Each processor has a priority assigned: the higher the priority, the more stringent the timing requirements. The slowdown can be controlled by regulating with precision the maximum amount of system bandwidth each processor is allowed to use, based on its priority. The proposed mechanism finds the maximum bandwidth each processor can use such that the highest number of processors simultaneously accessing memory is found (thus avoiding memory bandwidth underutilization) while guaranteeing that the slowdown of each processor is kept within the tolerated limits.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time operating systems
  • Heterogenous systems
  • Parallel execution
  • Shared memory
  • Bandwidth regulation
  • Memory access
  • Real-time execution
  • Memory bandwidth utilization
  • High Memory Bandwidth (HMB)
  • Memory access slowdown
  • Memory interference
  • Memory-centric scheduling


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