Volume
OASIcs, Volume 117
Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)
-
Part of:
Series:
Open Access Series in Informatics (OASIcs)
Conference: Workshop on Next Generation Real-Time Embedded Systems (NG-RES)
Event
NG-RES 2024, January 17-19, 2024, Munich, GermanyEditors
Publication Details
- published at: 2024-03-04
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-313-3
- DBLP: db/conf/hipeac/ngres2024
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Document
Complete Volume
OASIcs, Volume 117, NG-RES 2024, Complete Volume
Abstract
OASIcs, Volume 117, NG-RES 2024, Complete Volume
Cite as
Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 1-62, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@Proceedings{yomsi_et_al:OASIcs.NG-RES.2024,
title = {{OASIcs, Volume 117, NG-RES 2024, Complete Volume}},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
pages = {1--62},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-313-3},
ISSN = {2190-6807},
year = {2024},
volume = {117},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024},
URN = {urn:nbn:de:0030-drops-197028},
doi = {10.4230/OASIcs.NG-RES.2024},
annote = {Keywords: OASIcs, Volume 117, NG-RES 2024, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{yomsi_et_al:OASIcs.NG-RES.2024.0,
author = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-313-3},
ISSN = {2190-6807},
year = {2024},
volume = {117},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.0},
URN = {urn:nbn:de:0030-drops-197032},
doi = {10.4230/OASIcs.NG-RES.2024.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Invited Paper
HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper)
Abstract
Current homogeneous and heterogeneous computing systems reach high performance through parallelization. Yet, parallel execution of tasks entails non-trivial latency-vs-throughput issues when it comes to concurrent accesses to shared memory. In this respect, effective bandwidth regulation solutions do exist, and provide a basic mechanism to control the latency of memory accesses. Such solutions, though, are often cumbersome to deploy and to configure to guarantee both bounded latency and high utilization of the memory bandwidth. The problem is that memory latency varies non-linearly with the number and type of concurrent accesses, and the latter may in turn vary with time, often unpredictably. For this reason, previous attempts at memory regulation in scheduling solutions resulted either in poor real-time execution guarantees, or in severe underutilization of the memory bandwidth. In this paper, we outline High Memory Bandwidth (HMB), a scheduling solution that guarantees bounded response times to real-time task sets through memory regulation, while also reaching a high utilization memory bandwidth. Since the complete solution is complex, just like the problem it addresses, this preliminary work defines in full detail only the core mechanism. This mechanism builds on the notion of memory access slowdown experienced by any processor performing back-to-back memory operations; this slowdown is due to the interference generated by other processors also accessing the memory at the same time. The core mechanism assumes that each processor can tolerate a certain amount of slowdown before the timing behavior of the task(s) it is running is compromised. Each processor has a priority assigned: the higher the priority, the more stringent the timing requirements. The slowdown can be controlled by regulating with precision the maximum amount of system bandwidth each processor is allowed to use, based on its priority. The proposed mechanism finds the maximum bandwidth each processor can use such that the highest number of processors simultaneously accessing memory is found (thus avoiding memory bandwidth underutilization) while guaranteeing that the slowdown of each processor is kept within the tolerated limits.
Cite as
Mohammadhassan Gholami Derouei, Paolo Valente, Marco Solieri, and Andrea Marongiu. HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 1:1-1:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{gholamiderouei_et_al:OASIcs.NG-RES.2024.1,
author = {Gholami Derouei, Mohammadhassan and Valente, Paolo and Solieri, Marco and Marongiu, Andrea},
title = {{HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth}},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
pages = {1:1--1:18},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-313-3},
ISSN = {2190-6807},
year = {2024},
volume = {117},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.1},
URN = {urn:nbn:de:0030-drops-197049},
doi = {10.4230/OASIcs.NG-RES.2024.1},
annote = {Keywords: Heterogenous systems, Parallel execution, Shared memory, Bandwidth regulation, Memory access, Real-time execution, Memory bandwidth utilization, High Memory Bandwidth (HMB), Memory access slowdown, Memory interference, Memory-centric scheduling}
}
Document
Invited Paper
A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control (Invited Paper)
Abstract
Traffic congestion is one of the growing urban problem with associated problems like fuel wastage, loss of lives, and slow productivity. The existing traffic system uses programming logic control (PLC) with round-robin scheduling algorithm. Recent works have proposed IoT-based frameworks that use traffic density of each lane to control traffic movement, but they suffer from low accuracy due to lack of emergency vehicle image datasets for training deep neural networks. In this paper, we propose a novel distributed IoT framework that is based on two observations. The first observation is major structural changes to road are rare. This observation is exploited by proposing a novel two stage vehicle detector that is able to achieve 77% vehicle detection accuracy on UA-DETRAC dataset. The second observation is emergency vehicle have distinct siren sound that is detected using a novel acoustic detection algorithm on an edge device. The proposed system is able to detect emergency vehicles with an average accuracy of 99.4%.
Cite as
Zeba Khanam, Vejey Pradeep Suresh Achari, Issam Boukhennoufa, Anish Jindal, and Amit Kumar Singh. A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 2:1-2:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{khanam_et_al:OASIcs.NG-RES.2024.2,
author = {Khanam, Zeba and Achari, Vejey Pradeep Suresh and Boukhennoufa, Issam and Jindal, Anish and Singh, Amit Kumar},
title = {{A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control}},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
pages = {2:1--2:10},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-313-3},
ISSN = {2190-6807},
year = {2024},
volume = {117},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.2},
URN = {urn:nbn:de:0030-drops-197057},
doi = {10.4230/OASIcs.NG-RES.2024.2},
annote = {Keywords: Vehicle Detection, Deep Neural Network, Traffic Control, Edge Computing, Emergency Vehicle Detection, Sliding Window}
}
Document
Invited Paper
DynaVLC - Towards Dynamic GTS Allocation in VLC Networks (Invited Paper)
Abstract
Envisioned to deliver superior Quality of Service (QoS) by offering faster data rates and reduced latency in 6G communication scenarios, pioneering communication protocols like the IEEE 802.15.7 are poised to facilitate emerging application trends (e.g. metaverse). The IEEE 802.15.7 standard that supports visible light communication (VLC) provides determinism for time-critical reliable communication through its guaranteed time-slots mechanism of the contention-free period (CFP) while supporting non-time-critical communication through contention-access period (CAP). Nevertheless, the IEEE 802.15.7 MAC structure is fixed and statically defined at the beginning of the network creation. This rigid definition of the network can be detrimental when the traffic characteristics evolve dynamically, for example, due to environmental or user-driven workload conditions. To this purpose, this paper proposes a resource-aware dynamic architecture for IEEE 802.15.7 networks that efficiently adapts the superframe structure to traffic dynamics. Notably, this technique was shown to reduce the overall delay and throughput by up to 45% and 30%, respectively, when compared to the traditional IEEE 802.15.7 protocol performance under the same network conditions.
Cite as
Harrison Kurunathan, Miguel Gutiérrez Gaitán, Ramiro Sámano-Robles, and Eduardo Tovar. DynaVLC - Towards Dynamic GTS Allocation in VLC Networks (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 3:1-3:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{kurunathan_et_al:OASIcs.NG-RES.2024.3,
author = {Kurunathan, Harrison and Gait\'{a}n, Miguel Guti\'{e}rrez and S\'{a}mano-Robles, Ramiro and Tovar, Eduardo},
title = {{DynaVLC - Towards Dynamic GTS Allocation in VLC Networks}},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
pages = {3:1--3:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-313-3},
ISSN = {2190-6807},
year = {2024},
volume = {117},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.3},
URN = {urn:nbn:de:0030-drops-197069},
doi = {10.4230/OASIcs.NG-RES.2024.3},
annote = {Keywords: IEEE 802.15.7, VLC networks, network tuning}
}
Document
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs
Abstract
Embedded system applications usually have requirements regarding non-functional properties of their execution like latency or power consumption. Enforcement of such requirements can be implemented by a reactive control loop, where an enforcer determines based on a system response (feedback) how to control the system, e.g., by selecting the number of active cores allocated to a program or by scaling their voltage/frequency mode. It is of a particular interest to design enforcement strategies for which it is possible to provide formal guarantees with respect to requirement violations, especially under a largely varying environmental input (workload) per execution. In this paper, we consider enforcement strategies that are modeled by a finite state machine (FSM) and the environment by a discrete-time Markov chain. Such a formalization enables the formal verification of temporal properties (verification goals) regarding the satisfaction of requirements of a given enforcement strategy.
In this paper, we propose history-based enforcement FSMs which compute a reaction not just on the current, but on a fixed history of K previously observed system responses. We then analyze the quality of such enforcement FSMs in terms of the probability of satisfying a given set of verification goals and compare them to enforcement FSMs that react solely on the current system response. As experimental results, we present three use cases while considering requirements on latency and power consumption. The results show that history-based enforcement FSMs outperform enforcement FSMs that only consider the current system response regarding the probability of satisfying a given set of verification goals.
Cite as
Khalil Esper and Jürgen Teich. History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 4:1-4:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{esper_et_al:OASIcs.NG-RES.2024.4,
author = {Esper, Khalil and Teich, J\"{u}rgen},
title = {{History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs}},
booktitle = {Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
pages = {4:1--4:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-313-3},
ISSN = {2190-6807},
year = {2024},
volume = {117},
editor = {Yomsi, Patrick Meumeu and Wildermann, Stefan},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.4},
URN = {urn:nbn:de:0030-drops-197074},
doi = {10.4230/OASIcs.NG-RES.2024.4},
annote = {Keywords: Verification, Runtime Requirement Enforcement, History, Latency}
}