@InProceedings{amirshahi_et_al:OASIcs.PARMA-DITAM.2024.2, author = {Amirshahi, Alireza and Ansaloni, Giovanni and Atienza, David}, title = {{Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures}}, booktitle = {15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024)}, pages = {2:1--2:13}, series = {Open Access Series in Informatics (OASIcs)}, ISBN = {978-3-95977-307-2}, ISSN = {2190-6807}, year = {2024}, volume = {116}, editor = {Bispo, Jo\~{a}o and Xydis, Sotirios and Curzel, Serena and Sousa, Lu{\'\i}s Miguel}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2024.2}, URN = {urn:nbn:de:0030-drops-196960}, doi = {10.4230/OASIcs.PARMA-DITAM.2024.2}, annote = {Keywords: Memory arrangement, Data layout, Hardware accelerators, Transformer models, Multi-core, System simulation} }
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