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Accelerating GPGPU Simulation by Strategically Parallelizing the Compute Bottleneck

Authors Jakob Sachs, Tim Lühnen, Sohan Lal

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Document Identifiers

Subject Classification

ACM Subject Classification
  • Computing methodologies → Parallel programming languages
  • Computing methodologies → Simulation tools
  • Computer systems organization → Parallel architectures
Keywords
  • GPGPU
  • CUDA
  • Simulation
  • Computer Architecture
  • GPGPU-Sim
  • Parallel Simulation
  • Cycle-Accurate Simulation
  • Thread Pool

Metrics

Abstract

Cycle-accurate GPGPU simulators like GPGPU-Sim provide invaluable insights for hardware architecture research but suffer from extremely long runtimes, hindering research productivity. This paper addresses this critical bottleneck by proposing a strategy to accelerate GPGPU-Sim. We first perform a holistic profiling analysis across diverse GPGPU benchmarks to identify the primary performance bottleneck, pinpointing the SIMT-Core cluster execution within the CORE-clock cycle. Based on this, we implement a parallelization scheme that strategically targets this hotspot, utilizing a thread pool to manage concurrent execution of SIMT-Core clusters. Our approach prioritizes minimal modifications to the existing GPGPU-Sim codebase to ensure long-term maintainability. Evaluation of a simulated NVIDIA H100 model demonstrates an average simulation wall-time speedup of 3.58× with 8 worker threads, and a maximum up to 4.38×, while incurring a maximum cycle count error of 3.22%, with some other benchmarks exhibiting no error at all.

Cite As Get BibTex

Jakob Sachs, Tim Lühnen, and Sohan Lal. Accelerating GPGPU Simulation by Strategically Parallelizing the Compute Bottleneck. In 17th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 15th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2026). Open Access Series in Informatics (OASIcs), Volume 141, pp. 6:1-6:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2026.6

Author Details

Jakob Sachs
  • Hamburg University of Technology, Germany
Tim Lühnen
  • Hamburg University of Technology, Germany
Sohan Lal
  • Hamburg University of Technology, Germany

Supplementary Materials

References

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