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Linking High-Level Synthesis with FPGA Runtime Orchestration

Authors Despoina Tomkou , Aggelos Ferikoglou , Dimosthenis Masouros , Sotirios Xydis , Dimitrios Soudris

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Document Identifiers

Subject Classification

ACM Subject Classification
  • Computing methodologies
  • Computer systems organization → Cloud computing
  • Computer systems organization → Heterogeneous (hybrid) systems
  • Hardware → Emerging architectures
Keywords
  • FPGA
  • Orchestration
  • Partial Reconfiguration
  • FPGAaaS

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Abstract

FPGAs are increasingly being adopted across the edge-to-cloud continuum due to their ability to provide both high performance and energy efficiency. However, the complexity of programming FPGAs often leads to deployed designs that underutilize available resources. FPGA multi-tenancy has been proposed to enhance resource utilization, yet monolithic designs and dynamic workload demands continue to challenge efficient FPGA usage and compliance with Quality of Service requirements. To address these issues, we propose a novel framework for the optimal orchestration of FPGAs across the edge-to-cloud continuum while meeting user demands. The framework generates approximations of Pareto-optimal designs for each application, capturing trade-offs between performance and resource usage with minimal bitstream generation. This information allows the runtime orchestrator to select the most suitable design based on available PR regions and the QoS requirements of each user. Experimental results demonstrate that the proposed approach achieves an average reduction of QoS violations by a factor of 8.1× across diverse workloads and baseline configurations. Overall, the framework offers a practical and effective solution for realizing FPGA-as-a-Service across the edge-to-cloud continuum.

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Despoina Tomkou, Aggelos Ferikoglou, Dimosthenis Masouros, Sotirios Xydis, and Dimitrios Soudris. Linking High-Level Synthesis with FPGA Runtime Orchestration. In 17th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 15th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2026). Open Access Series in Informatics (OASIcs), Volume 141, pp. 7:1-7:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026) https://doi.org/10.4230/OASIcs.PARMA-DITAM.2026.7

Author Details

Despoina Tomkou
  • Microprocessors and Digital Systems Laboratory, ECE, NTUA, Athens, Greece
Aggelos Ferikoglou
  • Microprocessors and Digital Systems Laboratory, ECE, NTUA, Athens, Greece
Dimosthenis Masouros
  • Microprocessors and Digital Systems Laboratory, ECE, NTUA, Athens, Greece
Sotirios Xydis
  • Microprocessors and Digital Systems Laboratory, ECE, NTUA, Athens, Greece
Dimitrios Soudris
  • Microprocessors and Digital Systems Laboratory, ECE, NTUA, Athens, Greece

Funding

This work has been partially funded by the EU Horizon 2022 program under grant agreement No 101096698 REFMAP (https://www.refmap.eu/).

Supplementary Materials

References

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