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<h2>DARTS, Volume 5, Issue 1, ECRTS 2019</h2>
<ul>
<li>
    <span class="authors">Sophie Quinton, Sebastian Altmeyer, and Alessandro Papadopoulos</span>
    <span class="title">Front Matter - ECRTS 2019 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.0">10.4230/DARTS.5.1.0</a>
</li>
<li>
    <span class="authors">Pontus Ekberg</span>
    <span class="title">Dual Priority Scheduling is Not Optimal (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.1">10.4230/DARTS.5.1.1</a>
</li>
<li>
    <span class="authors">Corey Tessler and Nathan Fisher</span>
    <span class="title">NPM-BUNDLE: Non-Preemptive Multitask Scheduling for Jobs with BUNDLE-Based Thread-Level Scheduling (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.2">10.4230/DARTS.5.1.2</a>
</li>
<li>
    <span class="authors">Paolo Pazzaglia, Claudio Mandrioli, Martina Maggio, and Anton Cervin</span>
    <span class="title">DMAC: Deadline-Miss-Aware Control (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.3">10.4230/DARTS.5.1.3</a>
</li>
<li>
    <span class="authors">Roberto Cavicchioli, Nicola Capodieci, Marco Solieri, and Marko Bertogna</span>
    <span class="title">API Comparison of CPU-To-GPU Command Offloading Latency on Embedded Platforms (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.4">10.4230/DARTS.5.1.4</a>
</li>
<li>
    <span class="authors">Daniel Casini, Tobias Blaß, Ingo Lütkebohle, and Björn B. Brandenburg</span>
    <span class="title">Response-Time Analysis of ROS 2 Processing Chains Under Reservation-Based Scheduling (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.5">10.4230/DARTS.5.1.5</a>
</li>
<li>
    <span class="authors">Jian-Jia Chen, Tobias Hahn, Ruben Hoeksma, Nicole Megow, and Georg von der Brüggen</span>
    <span class="title">Scheduling Self-Suspending Tasks: New and Old Results (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.6">10.4230/DARTS.5.1.6</a>
</li>
<li>
    <span class="authors">Nathanaël Sensfelder, Julien Brunel, and Claire Pagetti</span>
    <span class="title">Modeling Cache Coherence to Expose Interference (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.7">10.4230/DARTS.5.1.7</a>
</li>
<li>
    <span class="authors">Sims Hill Osborne, Joshua J. Bakita, and James H. Anderson</span>
    <span class="title">Simultaneous Multithreading Applied to Real Time (Artifact)</span>
    <a class="doi" href="https://doi.org/10.4230/DARTS.5.1.8">10.4230/DARTS.5.1.8</a>
</li>
</ul>

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