Issue
Leibniz Transactions on Embedded Systems, Volume 2, Issue 1
LITES, Volume 2, Issue 1
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LITES, Volume 2
Journal: Leibniz Transactions on Embedded Systems (LITES)
Publication Details
- published at: 2015-06-01
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- DBLP: db/journals/lites/lites2
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Complete Issue
LITES, Volume 2, Issue 1
Abstract
LITES, Volume 2, Issue 1
Cite as
LITES, Volume 2, Issue 1, pp. 1-34, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2015)
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@Article{LITES-v002-i001,
title = {{LITES, Volume 2, Issue 1}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {1--34},
ISSN = {2199-2002},
year = {2015},
volume = {2},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v002-i001},
doi = {10.4230/LITES-v002-i001},
annote = {Keywords: LITES, Volume 2, Issue 1}
}
Document
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems
Abstract
Cache randomization per se, and its viability for probabilistic timing analysis (PTA) of critical real-time systems, are receiving increasingly close attention from the scientific community and the industrial practitioners. In fact, the very notion of introducing randomness and probabilities in time-critical systems has caused strenuous debates owing to the apparent clash that this idea has with the strictly deterministic view traditionally held for those systems. A paper recently appeared in LITES (Reineke, J. (2014). Randomized Caches Considered Harmful in Hard Real-Time Systems. LITES, 1(1), 03:1-03:13.) provides a critical analysis of the weaknesses and risks entailed in using randomized caches in hard real-time systems. In order to provide the interested reader with a fuller, balanced appreciation of the subject matter, a critical analysis of the benefits brought about by that innovation should be provided also. This short paper addresses that need by revisiting the array of issues addressed in the cited work, in the light of the latest advances to the relevant state of the art. Accordingly, we show that the potential benefits of randomized caches do offset their limitations, causing them to be - when used in conjunction with PTA - a serious competitor to conventional designs.
Cite as
Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, and Francisco J. Cazorla. Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems. In LITES, Volume 2, Issue 1 (2015). Leibniz Transactions on Embedded Systems, Volume 2, Issue 1, pp. 01:1-01:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2015)
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@Article{mezzetti_et_al:LITES-v002-i001-a001,
author = {Mezzetti, Enrico and Ziccardi, Marco and Vardanega, Tullio and Abella, Jaume and Qui\~{n}ones, Eduardo and Cazorla, Francisco J.},
title = {{Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {01:1--01:10},
ISSN = {2199-2002},
year = {2015},
volume = {2},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v002-i001-a001},
doi = {10.4230/LITES-v002-i001-a001},
annote = {Keywords: Real-time systems, Probabilistic WCET, Randomized caches}
}
Document
More General Optimal Offset Assignment
Abstract
This manuscript presents exact approaches to the general offset assignment problem arising in the address code generation phase of compilers for application-specific processors. First, integer programming models for architecture-dependent and theoretically motivated special cases of the problem are established. Then, these models are extended to provide the first widely applicable formulations for the most general problem setting, supporting processors with several address registers and complex addressing capabilities. Existing heuristics are similarly extended and practical applicability of the proposed methods is demonstrated by experimental evaluation using an established and large benchmark set. The experiments allow us to study the impact of exploiting more complex memory addressing capabilities on the address computation costs of real-world programs. We also show how to integrate operand reordering techniques for commutative instructions into existing solution approaches.
Cite as
Sven Mallach. More General Optimal Offset Assignment. In LITES, Volume 2, Issue 1 (2015). Leibniz Transactions on Embedded Systems, Volume 2, Issue 1, pp. 02:1-02:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2015)
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@Article{mallach:LITES-v002-i001-a002,
author = {Mallach, Sven},
title = {{More General Optimal Offset Assignment}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {02:1--02:18},
ISSN = {2199-2002},
year = {2015},
volume = {2},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v002-i001-a002},
doi = {10.4230/LITES-v002-i001-a002},
annote = {Keywords: Compiler optimization, Application-specific processors, Address code generation, Offset assignment, Integer programming}
}