<h2>Dagstuhl Seminar Proceedings, Volume 10281, </h2> <ul> <li> <span class="authors">Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede</span> <span class="title">10281 Abstracts Collection – Dynamically Reconfigurable Architectures</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.1">10.4230/DagSemProc.10281.1</a> </li> <li> <span class="authors">Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede</span> <span class="title">10281 Summary – Dynamically Reconfigurable Architectures</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.2">10.4230/DagSemProc.10281.2</a> </li> <li> <span class="authors">Gerard J. M. Smit, Jan Kuper, and Christiaan P. R. Baaij</span> <span class="title">A mathematical approach towards hardware design</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.3">10.4230/DagSemProc.10281.3</a> </li> <li> <span class="authors">Jim Torresen and Dirk Koch</span> <span class="title">A new project to address run-time reconfigurable hardware systems</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.4">10.4230/DagSemProc.10281.4</a> </li> <li> <span class="authors">Dirk Koch</span> <span class="title">Advances in Component-based System Design and Partial Run-time Reconfiguration</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.5">10.4230/DagSemProc.10281.5</a> </li> <li> <span class="authors">Jens Huthmann, Peter Müller, Florian Stock, Dietmar Hildenbrand, and Andreas Koch</span> <span class="title">Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.6">10.4230/DagSemProc.10281.6</a> </li> <li> <span class="authors">Norbert Abel</span> <span class="title">Design and Implementation of an Object-Oriented DPR-Framework</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.7">10.4230/DagSemProc.10281.7</a> </li> <li> <span class="authors">Walter Stechele, Christopher Claus, and Andreas Laika</span> <span class="title">Lessons Learned from last 4 Years of Reconfigurable Computing</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.8">10.4230/DagSemProc.10281.8</a> </li> <li> <span class="authors">Matthias Hanke, Tim Kranich, Mladen Berekovic, and Yannis Papaefstathiou</span> <span class="title">Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.9">10.4230/DagSemProc.10281.9</a> </li> <li> <span class="authors">Daniel Ziener and Jürgen Teich</span> <span class="title">New Directions for IP Core Watermarking and Identification</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.10">10.4230/DagSemProc.10281.10</a> </li> <li> <span class="authors">Nele Mentens, Jo Vliegen, An Braeken, Abdellah Touhafi, Karel Wouters, and Ingrid Verbauwhede</span> <span class="title">Secure remote reconfiguration of FPGAs</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.11">10.4230/DagSemProc.10281.11</a> </li> <li> <span class="authors">Xiaolei Chen and Yajun Ha</span> <span class="title">The Optimization of Interconnection Networks in FPGAs</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.12">10.4230/DagSemProc.10281.12</a> </li> <li> <span class="authors">Rene Cumplido, Juan Manuel Campos, Claudia Feregrino-Uribe, and Jose Roberto Perez-Andrade</span> <span class="title">Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.13">10.4230/DagSemProc.10281.13</a> </li> <li> <span class="authors">Branislav Hredzak and Oliver Diessel</span> <span class="title">Towards Dilated Placement of Dynamic NoC Cores</span> <a class="doi" href="https://doi.org/10.4230/DagSemProc.10281.14">10.4230/DagSemProc.10281.14</a> </li> </ul>
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