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<h2>OASIcs, Volume 55, WCET 2016</h2>
<ul>
<li>
    <span class="authors">Martin Schoeberl</span>
    <span class="title">OASIcs, Volume 55, WCET&#039;16, Complete Volume</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016">10.4230/OASIcs.WCET.2016</a>
</li>
<li>
    <span class="authors">Martin Schoeberl</span>
    <span class="title">Front Matter, Table of Contents, Preface, List of Authors, Committee</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.0">10.4230/OASIcs.WCET.2016.0</a>
</li>
<li>
    <span class="authors">Enrique Díaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-Askasua, Tullio Vardanega, and Francisco J. Cazorla</span>
    <span class="title">Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.1">10.4230/OASIcs.WCET.2016.1</a>
</li>
<li>
    <span class="authors">Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann, and Simon Wegener</span>
    <span class="title">TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.2">10.4230/OASIcs.WCET.2016.2</a>
</li>
<li>
    <span class="authors">Vincent Mussot, Jordy Ruiz, Pascal Sotin, Marianne de Michiel, and Hugues Cassé</span>
    <span class="title">Expressing and Exploiting Conflicts over Paths in WCET Analysis</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.3">10.4230/OASIcs.WCET.2016.3</a>
</li>
<li>
    <span class="authors">Boris Dreyer, Christian Hochberger, Alexander Lange, Simon Wegener, and Alexander Weiss</span>
    <span class="title">Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.4">10.4230/OASIcs.WCET.2016.4</a>
</li>
<li>
    <span class="authors">Amine Naji and Florian Brandner</span>
    <span class="title">Eager Stack Cache Memory Transfers</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.5">10.4230/OASIcs.WCET.2016.5</a>
</li>
<li>
    <span class="authors">Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho</span>
    <span class="title">The Variability of Application Execution Times on a Multi-Core Platform</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.6">10.4230/OASIcs.WCET.2016.6</a>
</li>
<li>
    <span class="authors">Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, and Sébastien Faucou</span>
    <span class="title">BEST: a Binary Executable Slicing Tool</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.7">10.4230/OASIcs.WCET.2016.7</a>
</li>
<li>
    <span class="authors">Wei-Tsun Sun and Hugues Cassé</span>
    <span class="title">Dynamic Branch Resolution Based on Combined Static Analyses</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.8">10.4230/OASIcs.WCET.2016.8</a>
</li>
<li>
    <span class="authors">Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quinones, Jaume Abella, Tullio Vardanega, and Francisco J. Cazorla</span>
    <span class="title">Measurement-Based Timing Analysis of the AURIX Caches</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.9">10.4230/OASIcs.WCET.2016.9</a>
</li>
<li>
    <span class="authors">Martin Frieb, Alexander Stegmeier, Jörg Mische, and Theo Ungerer</span>
    <span class="title">Employing MPI Collectives for Timing Analysis on Embedded Multi-Cores</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.10">10.4230/OASIcs.WCET.2016.10</a>
</li>
<li>
    <span class="authors">Christine Rochange</span>
    <span class="title">Parallel Real-Time Tasks, as Viewed by WCET Analysis and Task Scheduling Approaches</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.11">10.4230/OASIcs.WCET.2016.11</a>
</li>
<li>
    <span class="authors">Andreas Löfwenmark and Simin Nadjm-Tehrani</span>
    <span class="title">Understanding Shared Memory Bank Access Interference in Multi-Core Avionics</span>
    <a class="doi" href="https://doi.org/10.4230/OASIcs.WCET.2016.12">10.4230/OASIcs.WCET.2016.12</a>
</li>
</ul>

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