Published in: LIPIcs, Volume 260, 8th International Conference on Formal Structures for Computation and Deduction (FSCD 2023)
Thomas Ehrhard, Claudia Faggian, and Michele Pagani. The Sum-Product Algorithm For Quantitative Multiplicative Linear Logic. In 8th International Conference on Formal Structures for Computation and Deduction (FSCD 2023). Leibniz International Proceedings in Informatics (LIPIcs), Volume 260, pp. 8:1-8:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
@InProceedings{ehrhard_et_al:LIPIcs.FSCD.2023.8, author = {Ehrhard, Thomas and Faggian, Claudia and Pagani, Michele}, title = {{The Sum-Product Algorithm For Quantitative Multiplicative Linear Logic}}, booktitle = {8th International Conference on Formal Structures for Computation and Deduction (FSCD 2023)}, pages = {8:1--8:18}, series = {Leibniz International Proceedings in Informatics (LIPIcs)}, ISBN = {978-3-95977-277-8}, ISSN = {1868-8969}, year = {2023}, volume = {260}, editor = {Gaboardi, Marco and van Raamsdonk, Femke}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.FSCD.2023.8}, URN = {urn:nbn:de:0030-drops-179926}, doi = {10.4230/LIPIcs.FSCD.2023.8}, annote = {Keywords: Linear Logic, Proof-Nets, Denotational Semantics, Probabilistic Programming} }
Published in: DARTS, Volume 6, Issue 1, Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo. Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). In Special Issue of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Dagstuhl Artifacts Series (DARTS), Volume 6, Issue 1, pp. 4:1-4:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)
@Article{restuccia_et_al:DARTS.6.1.4, author = {Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio}, title = {{Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)}}, pages = {4:1--4:3}, journal = {Dagstuhl Artifacts Series}, ISSN = {2509-8195}, year = {2020}, volume = {6}, number = {1}, editor = {Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/DARTS.6.1.4}, URN = {urn:nbn:de:0030-drops-123941}, doi = {10.4230/DARTS.6.1.4}, annote = {Keywords: Heterogeneous computing, Predictable hardware acceleration, FPGA SoCs, Multi-Master architectures} }
Published in: LIPIcs, Volume 165, 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo. Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Leibniz International Proceedings in Informatics (LIPIcs), Volume 165, pp. 12:1-12:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)
@InProceedings{restuccia_et_al:LIPIcs.ECRTS.2020.12, author = {Restuccia, Francesco and Pagani, Marco and Biondi, Alessandro and Marinoni, Mauro and Buttazzo, Giorgio}, title = {{Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs}}, booktitle = {32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)}, pages = {12:1--12:23}, series = {Leibniz International Proceedings in Informatics (LIPIcs)}, ISBN = {978-3-95977-152-8}, ISSN = {1868-8969}, year = {2020}, volume = {165}, editor = {V\"{o}lp, Marcus}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2020.12}, URN = {urn:nbn:de:0030-drops-123753}, doi = {10.4230/LIPIcs.ECRTS.2020.12}, annote = {Keywords: Heterogeneous computing, Predictable hardware acceleration, FPGA SoCs, Multi-Master architectures} }
Published in: LIPIcs, Volume 133, 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)
Marco Pagani, Enrico Rossi, Alessandro Biondi, Mauro Marinoni, Giuseppe Lipari, and Giorgio Buttazzo. A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 24:1-24:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
@InProceedings{pagani_et_al:LIPIcs.ECRTS.2019.24, author = {Pagani, Marco and Rossi, Enrico and Biondi, Alessandro and Marinoni, Mauro and Lipari, Giuseppe and Buttazzo, Giorgio}, title = {{A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs}}, booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)}, pages = {24:1--24:24}, series = {Leibniz International Proceedings in Informatics (LIPIcs)}, ISBN = {978-3-95977-110-8}, ISSN = {1868-8969}, year = {2019}, volume = {133}, editor = {Quinton, Sophie}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.24}, URN = {urn:nbn:de:0030-drops-107611}, doi = {10.4230/LIPIcs.ECRTS.2019.24}, annote = {Keywords: AXI Bus, Bandwidth Reservation, Hardware Acceleration, FPGA} }
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