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nDimNoC: Real-Time D-dimensional NoC

Authors Yilian Ribot González , Geoffrey Nelissen , Eduardo Tovar

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Author Details

Yilian Ribot González
  • CISTER Research Centre, ISEP, Polytechnic Institute of Porto, Portugal
Geoffrey Nelissen
  • Eindhoven University of Technology, The Netherlands
Eduardo Tovar
  • CISTER Research Centre, ISEP, Polytechnic Institute of Porto, Portugal

Funding

This work was partially supported by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDP/UIDB 04234/2020); also by FCT and the ESF (European Social Fund) through the Regional Operational Programme (ROP) Norte 2020, under PhD grant 2020.06898.BD.

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Yilian Ribot González, Geoffrey Nelissen, and Eduardo Tovar. nDimNoC: Real-Time D-dimensional NoC. In 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). Leibniz International Proceedings in Informatics (LIPIcs), Volume 196, pp. 5:1-5:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
https://doi.org/10.4230/LIPIcs.ECRTS.2021.5

Abstract

The growing demand of powerful embedded systems to perform advanced functionalities led to a large increase in the number of computation nodes integrated in Systems-on-chip (SoC). In this context, network-on-chips (NoCs) emerged as a new standard communication infrastructure for multi-processor SoCs (MPSoCs). In this work, we present nDimNoC, a new D-dimensional NoC that provides real-time guarantees for systems implemented upon MPSoCs. Specifically, (1) we propose a new router architecture and a new deflection-based routing policy that use the properties of circulant topologies to ensure bounded worst-case communication delays, and (2) we develop a generic worst-case communication time (WCCT) analysis for packets transmitted over nDimNoC. In our experiments, we show that the WCCT of packets decreases when we increase the dimensionality of the NoC using nDimNoC’s topolgy and routing policy. By implementing nDimNoC in Verilog and synthesizing it for an FPGA platform, we show that a 3D-nDimNoC requires ≈5-times less silicon than routers that use virtual channels (VC). We computed the maximum operating frequency of a 3D-nDimNoC with Xilinx Vivado. Increasing the number dimensions in the NoC improves WCCT at the cost of a more complex routing logic that may result in a reduced operating clock frequency.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Networks → Network on chip
Keywords
  • Real-Time Embedded Systems
  • Systems-on-Chips
  • Network-on-Chips
  • Worst-Case Communication Time

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References

  1. P. Baran. On distributed communications networks. IEEE Transactions on Communications Systems, 12(1):1-9, 1964. URL: https://doi.org/10.1109/TCOM.1964.1088883.
  2. L. Benini and G. De Micheli. Networks on chip: a new paradigm for systems on chip design. In Design, Automation and Test in Europe Conference and Exhibition, pages 418-419, March 2002. Google Scholar
  3. Alan Burns, James Harbin, and Leandro Soares Indrusiak. A wormhole NoC protocol for mixed criticality systems. In IEEE Real-Time Systems Symposium, pages 184-195, 2014. Google Scholar
  4. Yiou Chen, Jianhao Hu, Xiang Ling, and Tingting Huang. A novel 3d noc architecture based on de bruijn graph. Computers & Electrical Engineering, 38(3):801-810, 2012. Google Scholar
  5. Shamik Das, Andy Fan, Kuan-Neng Chen, Chuan Seng Tan, Nisha Checka, and Rafael Reif. Technology, performance, and computer-aided design of three-dimensional integrated circuits. In Proceedings of the 2004 International Symposium on Physical Design, ISPD '04, page 108?115, New York, NY, USA, 2004. Association for Computing Machinery. URL: https://doi.org/10.1145/981066.981091.
  6. Dakshina Dasari, Borislav Nikoli'c, Vincent N'elis, and Stefan M Petters. NoC contention analysis using a branch-and-prune algorithm. ACM Transactions on Embedded Computing Systems, 13(3s):113, 2014. Google Scholar
  7. Jonas Diemer, Jonas Rox, Mircea Negrean, Steffen Stein, and Rolf Ernst. Real-time communication analysis for networks with two-stage arbitration. In 9th ACM International Conference on Embedded Software. IEEE, 2011. Google Scholar
  8. Feihui Li, C. Nicopoulos, T. Richardson, Yuan Xie, V. Narayanan, and M. Kandemir. Design and management of 3d chip multiprocessors using network-in-memory. In 33rd International Symposium on Computer Architecture (ISCA'06), pages 130-141, 2006. URL: https://doi.org/10.1109/ISCA.2006.18.
  9. Yan Ghidini, Thais Webber, Edson Moreno, Fernando Grando, Rubem Fagundes, and César Marcon. Buffer depth and traffic influence on 3d nocs performance. In 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), pages 9-15. IEEE, 2012. Google Scholar
  10. Frédéric Giroudot and Ahlem Mifdaoui. Buffer-aware worst-case timing analysis of wormhole NoCs using network calculus. In IEEE Real-Time and Embedded Technology and Applications Symposium, 2018. Google Scholar
  11. Frederic Giroudot and Ahlem Mifdaoui. Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip. In 27th International Conference on Real-Time Networks and Systems, 2019. Google Scholar
  12. C. Grecu, P. P. Pande, A. Ivanov, and R. Saleh. A scalable communication-centric soc interconnect architecture. In International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720), pages 343-348, 2004. URL: https://doi.org/10.1109/ISQED.2004.1283698.
  13. R. I. Greenberg and Lee Guan. An improved analytical model for wormhole routed networks with application to butterfly fat-trees. In Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162), pages 44-48, 1997. URL: https://doi.org/10.1109/ICPP.1997.622554.
  14. P. Guerrier and A. Greiner. A generic architecture for on-chip packet-switched interconnections. In Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pages 250-256, 2000. URL: https://doi.org/10.1109/DATE.2000.840047.
  15. Jörg Henkel, Wayne Wolf, and Srimat Chakradhar. On-chip networks: A scalable, communication-centric embedded system design paradigm. In 17th International Conference on VLSI Design. IEEE, 2004. Google Scholar
  16. S. Hesham, J. Rettkowski, D. Goehringer, and M. A. Abd El Ghany. Survey on real-time networks-on-chip. IEEE Transactions on Parallel and Distributed Systems, 28(5):1500-1517, May 2017. URL: https://doi.org/10.1109/TPDS.2016.2623619.
  17. Leandro Soares Indrusiak, Alan Burns, and Borislav Nikolić. Buffer-aware bounds to multi-point progressive blocking in priority-preemptive nocs. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 219-224. IEEE, 2018. Google Scholar
  18. Leandro Soares Indrusiak, James Harbin, and Alan Burns. Average and worst-case latency improvements in mixed-criticality wormhole networks-on-chip. In 27th Euromicro Conference on Real-Time Systems. IEEE, 2015. Google Scholar
  19. J. W. Joyner, P. Zarkesh-Ha, and J. D. Meindl. A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3d-soc). In Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558), pages 147-151, 2001. URL: https://doi.org/10.1109/ASIC.2001.954688.
  20. C. C. Liu, I. Ganusov, M. Burtscher, and Sandip Tiwari. Bridging the processor-memory performance gap with 3d ic technology. IEEE Design Test of Computers, 22(6):556-564, 2005. URL: https://doi.org/10.1109/MDT.2005.134.
  21. Meng Liu, Matthias Becker, Moris Behnam, and Thomas Nolte. Tighter time analysis for real-time traffic in on-chip networks with shared priorities. In 10th IEEE/ACM International Symposium on Networks-on-Chip, 2016. Google Scholar
  22. César Marcon, Ramon Fernandes, Rodrigo Cataldo, Fernando Grando, Thais Webber, Ana Benso, and Letícia B Poehls. Tiny noc: A 3d mesh topology with router channel optimization for area and latency minimization. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, pages 228-233. IEEE, 2014. Google Scholar
  23. Alireza Monemi, Jia Tang, Maurizio Palesi, and Muhammad Nadzir Marsono. ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. Microprocessors and Microsystems, 54, September 2017. URL: https://doi.org/10.1016/j.micpro.2017.08.007.
  24. B. Nikolic, Robin Hofmann, and R. Ernst. Slot-based transmission protocol for real-time nocs - sbt-noc. In ECRTS, 2019. Google Scholar
  25. B. Nikolić and S. M. Petters. Edf as an arbitration policy for wormhole-switched priority-preemptive nocs-myth or fact? In International Conference on Embedded Software, pages 1-10, October 2014. Google Scholar
  26. Borislav Nikolić, Sebastian Tobuschat, Leandro Soares Indrusiak, Rolf Ernst, and Alan Burns. Real-time analysis of priority-preemptive nocs with arbitrary buffer sizes and router delays. Real-Time Systems, 55(1):63-105, 2019. Google Scholar
  27. M. K. Papamichael and J. C. Hoe. CONNECT: Re-examining conventional wisdom for designing Nocs in the context of FPGAs. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '12, pages 37-46, New York, NY, USA, 2012. ACM. Google Scholar
  28. D. Park, S. Eachempati, R. Das, A. K. Mishra, Y. Xie, N. Vijaykrishnan, and C. R. Das. Mira: A multi-layered on-chip interconnect router architecture. In 2008 International Symposium on Computer Architecture, pages 251-261, 2008. URL: https://doi.org/10.1109/ISCA.2008.13.
  29. Vasilis F Pavlidis, Ioannis Savidis, and Eby G Friedman. Three-dimensional integrated circuit design. Newnes, 2017. Google Scholar
  30. Eberle A Rambo and Rolf Ernst. Worst-case communication time analysis of networks-on-chip with shared virtual channels. In Design, Automation & Test in Europe Conference & Exhibition, 2015. Google Scholar
  31. Y. Ribot González and G. Nelissen. Hoplitert*: Real-time noc for fpga. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11):3650-3661, 2020. URL: https://doi.org/10.1109/TCAD.2020.3012748.
  32. Aleksandr Yu Romanov. Development of routing algorithms in networks-on-chip based on ring circulant topologies. Heliyon, 5(4):e01516, 2019. Google Scholar
  33. Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch, et al. 3D integration for NoC-based SoC Architectures. Springer, 2011. Google Scholar
  34. Zheng Shi and Alan Burns. Real-time communication analysis for on-chip networks with wormhole switching. In Second ACM/IEEE International Symposium on Networks-on-Chip, 2008. Google Scholar
  35. Zheng Shi and Alan Burns. Improvement of schedulability analysis with a priority share policy in on-chip networks. In 17th International Conference on Real-Time and Network Systems, pages 75-84, 2009. Google Scholar
  36. Zheng Shi and Alan Burns. Real-time communication analysis with a priority share policy in on-chip networks. In 21st Euromicro Conference on Real-Time Systems, pages 3-12. IEEE, 2009. Google Scholar
  37. S. Tobuschat, P. Axer, R. Ernst, and J. Diemer. IDAMC: A NoC for mixed criticality systems. In IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013. URL: https://doi.org/10.1109/RTCSA.2013.6732214.
  38. Sebestian Tobuschat. Predictable and Runtime-Adaptable Network-On-Chip for Mixed-critical Real-time Systems. PhD thesis, TU Braunschweig, 2019. Google Scholar
  39. S. Wasly, R. Pellizzoni, and N. Kapre. HopliteRT: An efficient FPGA NoC for real-time applications. In International Conference on Field Programmable Technology, pages 64-71, December 2017. Google Scholar
  40. Saud Wasly, Rodolfo Pellizzoni, and Nachiket Kapre. Worst case latency analysis for hoplite FPGA-based NoC. Technical report, University of Waterloo, 2017. Google Scholar
  41. Qin Xiong, Zhonghai Lu, Fei Wu, and Changsheng Xie. Real-time analysis for wormhole noc: Revisited and revised. In Proceedings of the 26th edition on Great Lakes Symposium on VLSI, pages 75-80, 2016. Google Scholar
  42. Qin Xiong, Fei Wu, Zhonghai Lu, and Changsheng Xie. Extending real-time analysis for wormhole nocs. IEEE Transactions on Computers, 66(9):1532-1546, 2017. Google Scholar
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