Argyrides, Costas ;
Pradhan, Dhiraj K.
Multiple Event Upsets Aware FPGAs Using Protected Schemes
Abstract
Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in different parts to implement circuit configuration and to implement circuit data. Moreover, configuration bits of SRAM-based FPGAs are more sensible to upsets compared to circuit data due to significant number of SRAM bits. In this paper, a new protected Configurable Logic Block (CLB) and FPGA architecture are proposed which utilize multiple error correction (DEC) and multiple error detection. This is achieved by the incorporation of recently proposed coding technique Matrix codes [1] inside the FPGA. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.
BibTeX - Entry
@InProceedings{argyrides_et_al:DagSemProc.08371.6,
author = {Argyrides, Costas and Pradhan, Dhiraj K.},
title = {{Multiple Event Upsets Aware FPGAs Using Protected Schemes}},
booktitle = {Fault-Tolerant Distributed Algorithms on VLSI Chips},
pages = {1--15},
series = {Dagstuhl Seminar Proceedings (DagSemProc)},
ISSN = {1862-4405},
year = {2009},
volume = {8371},
editor = {Bernadette Charron-Bost and Shlomi Dolev and Jo Ebergen and Ulrich Schmid},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/opus/volltexte/2009/1926},
URN = {urn:nbn:de:0030-drops-19261},
doi = {10.4230/DagSemProc.08371.6},
annote = {Keywords: FPGA, SEUs, ECC, Reliability, MTTF}
}
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Keywords: |
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FPGA, SEUs, ECC, Reliability, MTTF |
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Seminar: |
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08371 - Fault-Tolerant Distributed Algorithms on VLSI Chips
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Issue date: |
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2009 |
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Date of publication: |
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13.03.2009 |
13.03.2009
