Multiple Event Upsets Aware FPGAs Using Protected Schemes

Authors Costas Argyrides, Dhiraj K. Pradhan



PDF
Thumbnail PDF

File

DagSemProc.08371.6.pdf
  • Filesize: 239 kB
  • 15 pages

Document Identifiers

Author Details

Costas Argyrides
Dhiraj K. Pradhan

Cite AsGet BibTex

Costas Argyrides and Dhiraj K. Pradhan. Multiple Event Upsets Aware FPGAs Using Protected Schemes. In Fault-Tolerant Distributed Algorithms on VLSI Chips. Dagstuhl Seminar Proceedings, Volume 8371, pp. 1-15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2009)
https://doi.org/10.4230/DagSemProc.08371.6

Abstract

Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in different parts to implement circuit configuration and to implement circuit data. Moreover, configuration bits of SRAM-based FPGAs are more sensible to upsets compared to circuit data due to significant number of SRAM bits. In this paper, a new protected Configurable Logic Block (CLB) and FPGA architecture are proposed which utilize multiple error correction (DEC) and multiple error detection. This is achieved by the incorporation of recently proposed coding technique Matrix codes [1] inside the FPGA. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.
Keywords
  • FPGA
  • SEUs
  • ECC
  • Reliability
  • MTTF

Metrics

  • Access Statistics
  • Total Accesses (updated on a weekly basis)
    0
    PDF Downloads
Questions / Remarks / Feedback
X

Feedback for Dagstuhl Publishing


Thanks for your feedback!

Feedback submitted

Could not send message

Please try again later or send an E-mail