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Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout

Authors Philipp Jungklass, Mladen Berekovic

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Author Details

Philipp Jungklass
  • IAV GmbH, Gifhorn, Germany
Mladen Berekovic
  • Universität zu Lübeck, Institute of Computer Engineering, Germany

Acknowledgements

Special thanks to Arne Bredemeier from Infineon.

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Philipp Jungklass and Mladen Berekovic. Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021) https://doi.org/10.4230/OASIcs.NG-RES.2021.3

Abstract

Modern microcontrollers for safety-critical real-time systems use a hierarchical memory system to increase execution speed and memory capacity. For this purpose, flash memories, which offer high capacity at low transfer rates, are combined with scratchpad memories, which provide high access speed at low memory capacities. The main goal is to use both types of memory in such a way that their advantages are optimally exploited. The target is to allocate runtime-intensive code fragments with low memory requirements to the fast scratchpad memories. Previous approaches to separate program code on system memories consider the executed functions as the smallest logical unit. This is contradicted by the fact that not all parts of a function have the same computing time in relation to their memory usage. This article introduces a procedure that automatically analyses the compiled source code and identifies runtime intensive fragments. For this purpose, the translated code is executed in an offline simulator and the maximum repetition for each instruction is detected. This information is used to create logical code fragments called basic blocks. This is repeated for all functions in the overall system. During the analysis of the functions, the dependencies between them are also extracted and a corresponding call-graph with the call frequencies is generated. By combining the information from the call graph and the evaluation of the basic blocks, a prognosis of the computing load of the respective code blocks is created, which serves as base for the distribution into the fast scratchpad memories. To verify the described procedure, EEMBC’s CoreMark is executed on an Infineon AURIX TC29x microcontroller, in which different scratchpad sizes are simulated. It is demonstrated that the allocation of basic blocks scales significantly better with smaller memory sizes than the previous function-based approach.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time system architecture
Keywords
  • Memory Architecture
  • Memory Management
  • Real-time Systems

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References

  1. N. Akram, Y. Zhang, S. Ali, and H. M. Amjad. Efficient task allocation for real-time partitioned scheduling on multi-core systems. In 2019 16th International Bhurban Conference on Applied Sciences and Technology (IBCAST), pages 492-499, 2019. URL: https://doi.org/10.1109/IBCAST.2019.8667139.
  2. Oren Avissar, Rajeev Barua, and Dave Stewart. An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Transactions on Embedded Computing Systems, 1(1):6-26, November 2002. Google Scholar
  3. Marco Caccamo, Marco Cesati, Rodolfo Pellizzoni, Emiliano Betti, Roman Dudko, and Renato Mancuso. Real-time cache management framework for multi-core architectures. In Proceedings of the 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE Computer Society, 2013. Google Scholar
  4. Zhong-Ho Chen and Alvin Su. A hardware/software framework for instruction and data scratchpad memory allocation. ACM Transactions on Architecture and Code Optimization, 7, April 2010. URL: https://doi.org/10.1145/1736065.1736067.
  5. C. Dietrich, P. Wägemann, P. Ulbrich, and D. Lohmann. Syswcet: Whole-system response-time analysis for fixed-priority real-time systems (outstanding paper). In 2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 37-48, 2017. Google Scholar
  6. Infineon Technologies AG, 81726 Munich, Germany. TriCore TC1.6P & TC1.6E Core Architecture, February 2012. Google Scholar
  7. Infineon Technologies AG, 81726 Munich, Germany. AURIX TC29x B-Step User’s Manual V1.3, December 2014. Google Scholar
  8. Philipp Jungklass and Mladen Berekovic. Effects of concurrent access to embedded multicore microcontrollers with hard real-time demands. In 2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES), pages 1-9, 2018. Google Scholar
  9. Philipp Jungklass and Mladen Berekovic. Intercore-kommunikation für multicore-mikrocontroller. In Tagungsband Embedded Software Engineering Kongress 2018, 2018. Google Scholar
  10. Philipp Jungklass and Mladen Berekovic. Memopt: Automated memory distribution for multicore microcontrollers with hard real-time requirements. In 2019 IEEE Nordic Circuits and Systems Conference (NORCAS), 2019. Google Scholar
  11. C. Kachris, G. Nikiforos, V. Papaefstathiou, X. Yang, S. Kavadias, and M. Katevenis. Low-latency explicit communication and synchronization in scalable multi-core clusters. In 2010 IEEE International Conference On Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), pages 1-4, 2010. Google Scholar
  12. Yooseong Kim, David Broman, Jian Cai, and Aviral Shrivastava. Wcet-aware dynamic code management on scratchpads for software-managed multicores. Real-Time Technology and Applications - Proceedings, 2014:179-188, October 2014. URL: https://doi.org/10.1109/RTAS.2014.6926001.
  13. Isabelle Puaut and Christophe Pais. Scratchpad memories vs locked caches in hard real-time systems: a qualitative and quantitative comparison. Institut de Recherche en Informatique et Systèmes Aléatoires - Publication Interne No 1818, January 2006. Google Scholar
  14. Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, and Benoît Dupont de Dinechin. The shift to multicores in real-time and safety-critical systems. In Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, pages 220-229. IEEE Press, 2015. Google Scholar
  15. STMicroelectronics, Schiphol, Amsterdam, Niederlande. SPC58xEx/SPC58xGx 32-bit Power Architecture microcontroller for automotive ASILD applications - Reference Manual, August 2018. Google Scholar
  16. V. Suhendra, T. Mitra, A. Roychoudhury, and Ting Chen. Wcet centric data allocation to scratchpad memory. In 26th IEEE International Real-Time Systems Symposium, pages 10 pp.-232, 2005. URL: https://doi.org/10.1109/RTSS.2005.45.
  17. TASKING BV, Spoetnik 50, 3824 MG Amersfoort, Netherlands. TASKING VX-toolset for TriCore User Guide, ma160-800 (v6.2) edition, December 2016. Google Scholar
  18. Texas Instruments Incorporated, Post Office Box 655303, Dallas, Texas 75265. TMS320F2838x Microcontrollers Technical Reference Manual, May 2019. Google Scholar
  19. G. Yao, R. Pellizzoni, S. Bak, H. Yun, and M. Caccamo. Global real-time memory-centric scheduling for multicore systems. IEEE Transactions on Computers, 65(9):2739-2751, 2016. URL: https://doi.org/10.1109/TC.2015.2500572.
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