OASIcs.NG-RES.2021.5.pdf
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M2OS-Mc: An RTOS for Many-Core Processors
Authors
David García Villaescusa 
,
Mario Aldea Rivas ,
Michael González Harbour
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Part of:
Volume:
Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)
Series: Open Access Series in Informatics (OASIcs)
Conference: Workshop on Next Generation Real-Time Embedded Systems (NG-RES) - License:
Creative Commons Attribution 3.0 Unported license
- Publication Date: 2021-01-14
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David García Villaescusa, Mario Aldea Rivas, and Michael González Harbour. M2OS-Mc: An RTOS for Many-Core Processors. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 5:1-5:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)
https://doi.org/10.4230/OASIcs.NG-RES.2021.5
Abstract
A current trend of industrial systems is reducing space, weight and power (SWaP) through the allocation of different applications on a single chip. This is enabled by the continued improvement of semiconductor technology which allows the integration of multiple cores in a single processor chip, as the processors are prevented to continue increasing their clock rate due to the "power-wall". The use of Commercial-Off-The-Shelf (COTS) multi-core processors for real-time purposes presents issues due to the shared bus used to access the shared memory. An alternative to the use of multi-core processors are the many-core processors with tens to hundreds of processors in the same chip, using different scalable ways to interconnect their cores. This paper presents the adaptation of the M2OS Real-Time Operating System (RTOS) and its simplified Ada run-time for mesh-based many-core processors. This RTOS is called M2OS-mc and has been tested on the Epiphany III many-core processor (referred in this paper simply as Epiphany), a many-core which has 16 cores connected by a Network-on-Chip (NoC) consisting of a 4x4 2D mesh. In order to have a synchronized way to send messages between tasks through the NoC independently of the core where they are being executed, we provide sampling port communication primitives.
Subject Classification
ACM Subject Classification
- Computer systems organization → Real-time operating systems
Keywords
- M2OS
- Many-Core
- Real-Time
- Parallella
- Epiphany
- Network-on-Chip
- Operating System
- RTOS
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References
- Mario Aldea-Rivas and Héctor Pérez-Tijero. Proposal for a new ada profile for small microcontrollers. Ada Lett., 38(1):34–39, July 2018. URL: https://doi.org/10.1145/3241950.3241955.
- Hesham Almatary. Operating System Kernels on Multi-core Architectures. PhD thesis, University of York, January 2016. URL: http://etheses.whiterose.ac.uk/12959/.
- Jorge Garrido Balaguer, Juan Rafael Zamorano Flores, and Juan Antonio de la Puente Alfaro. Arinc-653 inter-partition communications and the ravenscar profile. Ada Letters, 35(1):38-45, 2015. URL: http://oa.upm.es/42418/.
- Andrew Baumann, Paul Barham, Rebecca Isaacs, and Tim Harris. The multikernel: A new os architecture for scalable multicore systems. In 22nd Symposium on Operating Systems Principles. Association for Computing Machinery, Inc., October 2009. URL: https://www.microsoft.com/en-us/research/publication/the-multikernel-a-new-os-architecture-for-scalable-multicore-systems/.
- Luca Benini and Giovanni Micheli. Networks on chips: A new soc paradigm. Computer, 35:70-78, February 2002. URL: https://doi.org/10.1109/2.976921.
- Benoundefinedt Dupont de Dinechin and Amaury Graillat. Network-on-chip service guarantees on the kalray mppa-256 bostan processor. In Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS ’17, page 35–40, New York, NY, USA, 2017. Association for Computing Machinery. URL: https://doi.org/10.1145/3073763.3073770.
-
Erika Enterprise. Erika3. [Online; accessed 29-January-2020].
-
eSol. Scalable and High-performance Real-Time OS available for various types of processors. [Online; accessed 29-January-2020].
- Xiongli Gu, Peng Liu, Mei Yang, Jie Yang, Cheng Li, and Qingdong Yao. An efficient scheduler of rtos for multi/many-core system. Computers & Electrical Engineering, 38(3):785-800, 2012. The Design and Analysis of Wireless Systems and Emerging Computing Architectures and Systems. URL: https://doi.org/10.1016/j.compeleceng.2011.09.009.
- Salma Hesham, Jens Rettkowski, Diana Goehringer, and Mohamed A. Abd El Ghany. Survey on real-time networks-on-chip. IEEE Trans. Parallel Distrib. Syst., 28(5):1500–1517, May 2017. URL: https://doi.org/10.1109/TPDS.2016.2623619.
- Leandro Soares Indrusiak. End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. Journal of Systems Architecture, 60(7):553-561, 2014. URL: https://doi.org/10.1016/j.sysarc.2014.05.002.
-
James Jeffers and James Reinders. Intel Xeon Phi coprocessor high performance programming. Newnes, 2013.
- Borislav Nikolic, Sebastian Tobuschat, Leandro Indrusiak, Rolf Ernst, and Alan Burns. Real-time analysis of priority-preemptive nocs with arbitrary buffer sizes and router delays. Real-Time Systems, 55, June 2018. URL: https://doi.org/10.1007/s11241-018-9312-0.
-
Andreas Olofsson. Parallella reference manual.
-
Andreas Olofsson. Epiphany-v: A 1024 processor 64-bit risc system-on-chip. arXiv preprint arXiv:1610.01832, 2016.
- Andreas Olofsson, Tomas Nordström, and Zain Ul-Abdin. Kickstarting high-performance energy-efficient manycore architectures with epiphany. CoRR, 2014. URL: http://arxiv.org/abs/1412.5538.
- Mario Aldea Rivas and Hector Perez Tijero. Leveraging real-time and multitasking ada capabilities to small microcontrollers. Journal of Systems Architecture, 94:32-41, 2019. URL: https://doi.org/10.1016/j.sysarc.2019.02.015.