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nDimNoC: Real-Time D-dimensional NoC

Authors Yilian Ribot González , Geoffrey Nelissen , Eduardo Tovar

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Author Details

Yilian Ribot González
  • CISTER Research Centre, ISEP, Polytechnic Institute of Porto, Portugal
Geoffrey Nelissen
  • Eindhoven University of Technology, The Netherlands
Eduardo Tovar
  • CISTER Research Centre, ISEP, Polytechnic Institute of Porto, Portugal

Funding

This work was partially supported by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDP/UIDB 04234/2020); also by FCT and the ESF (European Social Fund) through the Regional Operational Programme (ROP) Norte 2020, under PhD grant 2020.06898.BD.

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Yilian Ribot González, Geoffrey Nelissen, and Eduardo Tovar. nDimNoC: Real-Time D-dimensional NoC. In 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). Leibniz International Proceedings in Informatics (LIPIcs), Volume 196, pp. 5:1-5:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021) https://doi.org/10.4230/LIPIcs.ECRTS.2021.5

Abstract

The growing demand of powerful embedded systems to perform advanced functionalities led to a large increase in the number of computation nodes integrated in Systems-on-chip (SoC). In this context, network-on-chips (NoCs) emerged as a new standard communication infrastructure for multi-processor SoCs (MPSoCs). In this work, we present nDimNoC, a new D-dimensional NoC that provides real-time guarantees for systems implemented upon MPSoCs. Specifically, (1) we propose a new router architecture and a new deflection-based routing policy that use the properties of circulant topologies to ensure bounded worst-case communication delays, and (2) we develop a generic worst-case communication time (WCCT) analysis for packets transmitted over nDimNoC. In our experiments, we show that the WCCT of packets decreases when we increase the dimensionality of the NoC using nDimNoC’s topolgy and routing policy. By implementing nDimNoC in Verilog and synthesizing it for an FPGA platform, we show that a 3D-nDimNoC requires ≈5-times less silicon than routers that use virtual channels (VC). We computed the maximum operating frequency of a 3D-nDimNoC with Xilinx Vivado. Increasing the number dimensions in the NoC improves WCCT at the cost of a more complex routing logic that may result in a reduced operating clock frequency.

Subject Classification

ACM Subject Classification
  • Computer systems organization → Real-time systems
  • Networks → Network on chip
Keywords
  • Real-Time Embedded Systems
  • Systems-on-Chips
  • Network-on-Chips
  • Worst-Case Communication Time

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